From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH v3 4/6] drm/i915: Remove the enabling of
 VS_TIMER_DISPATCH bit in MI MODE reg
Date: Tue, 25 Mar 2014 15:11:10 +0200
Message-ID: <20140325131110.GN21652@intel.com>
References: <20140325113351.GM21652@intel.com>
 <1395750710-30424-1-git-send-email-sourab.gupta@intel.com>
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To: sourab.gupta@intel.com
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, intel-gfx@lists.freedesktop.org, Akash Goel <akash.goel@intel.com>
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On Tue, Mar 25, 2014 at 06:01:50PM +0530, sourab.gupta@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> =

> This patch Removes the VS_TIMER_DISPATCH bit enable in MI MODE reg for
> platforms > Gen6.
> VS_TIMER_DISPATCH bit enable was earlier required as a part of
> WA 'WaTimedSingleVertexDispatch', which is now applicable only to
> platforms < Gen7.
> =

> v2: Enhancing the scope of the patch to full Gen7 (Chris)
> =

> v3: Modifying the WA condition to the cover the applicable platforms,
> and adding the WA name in comments. (Ville)
> =

> Signed-off-by: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> # ivb, hsw -Chris

Reviewed-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> =

> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9=
15/intel_ringbuffer.c
> index 816137f..2ad5fe7 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -605,7 +605,8 @@ static int init_render_ring(struct intel_ring_buffer =
*ring)
>  	struct drm_i915_private *dev_priv =3D dev->dev_private;
>  	int ret =3D init_ring_common(ring);
>  =

> -	if (INTEL_INFO(dev)->gen > 3)
> +	/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> +	if (INTEL_INFO(dev)->gen >=3D 4 && INTEL_INFO(dev)->gen < 7)
>  		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
>  =

>  	/* We need to disable the AsyncFlip performance optimisations in order
> -- =

> 1.8.5.1

-- =

Ville Syrj=E4l=E4
Intel OTC