From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH 1/2] drm/i915/bdw: Add WT caching ability Date: Sat, 29 Mar 2014 15:58:11 -0700 Message-ID: <20140329225810.GA15455@bwidawsk.net> References: <1396133802-15385-1-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail.bwidawsk.net (bwidawsk.net [166.78.191.112]) by gabe.freedesktop.org (Postfix) with ESMTP id 23F546EE32 for ; Sat, 29 Mar 2014 15:58:25 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1396133802-15385-1-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ben Widawsky Cc: Intel GFX List-Id: intel-gfx@lists.freedesktop.org On Sat, Mar 29, 2014 at 03:56:41PM -0700, Ben Widawsky wrote: > I don't have any insight on what parts can do what. The docs do seem to > suggest WT caching works in at least the same manner as it doesn't on > Haswell. > That's a freudian slip... s/doesn't/does/ > The addr = 0 is to shut up GCC: > drivers/gpu/drm/i915/i915_gem_gtt.c:80:7: warning: 'addr' may be used > uninitialized in this function [-Wmaybe-uninitialized] > > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_drv.h | 11 ++++++----- > drivers/gpu/drm/i915/i915_gem_gtt.c | 17 +++++++++++++---- > 2 files changed, 19 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index e23bb73..896fe8e 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1822,11 +1822,12 @@ struct drm_i915_cmd_table { > #define BSD_RING (1< #define BLT_RING (1< #define VEBOX_RING (1< -#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) > -#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) > -#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) > -#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) > -#define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) > +#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) > +#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) > +#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) > +#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) > +#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ > + to_i915(dev)->ellc_size) > #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) > > #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 4467974..10d00ee 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -68,10 +68,19 @@ static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, > { > gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; > pte |= addr; > - if (level != I915_CACHE_NONE) > - pte |= PPAT_CACHED_INDEX; > - else > + > + switch (level) { > + case I915_CACHE_NONE: > pte |= PPAT_UNCACHED_INDEX; > + break; > + case I915_CACHE_WT: > + pte |= PPAT_DISPLAY_ELLC_INDEX; > + break; > + default: > + pte |= PPAT_CACHED_INDEX; > + break; > + } > + > return pte; > } > > @@ -1367,7 +1376,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, > (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; > int i = 0; > struct sg_page_iter sg_iter; > - dma_addr_t addr; > + dma_addr_t addr = 0; > > for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { > addr = sg_dma_address(sg_iter.sg) + > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ben Widawsky, Intel Open Source Technology Center