From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/3] drm/i915: Implement sema idle msg disable for all rings Date: Mon, 31 Mar 2014 19:23:20 +0200 Message-ID: <20140331172320.GV22327@phenom.ffwll.local> References: <1396279038-28914-1-git-send-email-ville.syrjala@linux.intel.com> <1396279038-28914-3-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-we0-f173.google.com (mail-we0-f173.google.com [74.125.82.173]) by gabe.freedesktop.org (Postfix) with ESMTP id 91AD66E39C for ; Mon, 31 Mar 2014 10:23:24 -0700 (PDT) Received: by mail-we0-f173.google.com with SMTP id w61so5020909wes.4 for ; Mon, 31 Mar 2014 10:23:23 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1396279038-28914-3-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Mar 31, 2014 at 06:17:17PM +0300, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > Previously in > commit 295e8bb73a4785b65db6655fbf6ad57c4177b551 > Author: Ville Syrj=E4l=E4 > Date: Thu Feb 27 21:59:01 2014 +0200 > = > drm/i915: Disable semaphore wait event idle message on BDW > = > I failed to notice that all rings have their own copy of the bit that > disables the semaphore wait even idle message. So that patch only succeed= ed > in disabling it for the render ring. Instead we should set the bit for all > rings. > = > Signed-off-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++ > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_pm.c | 3 --- > 3 files changed, 10 insertions(+), 3 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_= gem.c > index 33bbaa0..84a7171 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4372,6 +4372,14 @@ static int i915_gem_init_rings(struct drm_device *= dev) > goto cleanup_blt_ring; > } > = > + if (IS_GEN8(dev)) { > + struct intel_ring_buffer *ring; > + int i; > + > + for_each_ring(ring, dev_priv, i) > + I915_WRITE(RING_RC_PSMI_CONTROL(ring), > + _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); > + } Why move this to here? Is this one of those bits which get reset on ring init? If that's the case I think we really need to have a w/a checker to make sure that after driver load, suspend/resume and gpu reset we always have the same set of workarounds ... -Daniel > = > ret =3D i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); > if (ret) > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 1f927a5..a47b4c3 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1068,6 +1068,8 @@ enum punit_power_well { > #define GEN6_BLITTER_LOCK_SHIFT 16 > #define GEN6_BLITTER_FBC_NOTIFY (1<<3) > = > +#define RING_RC_PSMI_CONTROL(ring) ((ring)->mmio_base + 0x50) > + > #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 > #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 9454a3c..21cfbc7 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4876,9 +4876,6 @@ static void gen8_init_clock_gating(struct drm_devic= e *dev) > I915_WRITE(GEN7_GT_MODE, > GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); > = > - I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, > - _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); > - > /* WaDisableSDEUnitClockGating:bdw */ > I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | > GEN8_SDEUNIT_CLOCK_GATE_DISABLE); > -- = > 1.8.3.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch