* [PATCH 1/3] drm/i915: Fix debugfs PDP register dump
2014-03-31 15:17 [PATCH 0/3] drm/i915: Gen8 workarounds and debugfs fix ville.syrjala
@ 2014-03-31 15:17 ` ville.syrjala
2014-04-02 17:28 ` Ben Widawsky
2014-03-31 15:17 ` [PATCH 2/3] drm/i915: Implement sema idle msg disable for all rings ville.syrjala
2014-03-31 15:17 ` [PATCH 3/3] drm/i915: Implement WaProgramMiArbOnOffAroundMiSetContext:bdw ville.syrjala
2 siblings, 1 reply; 10+ messages in thread
From: ville.syrjala @ 2014-03-31 15:17 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Iterate over all the PDP registers instead of just printing PDP0 four
times in gen8 PPGTT debugfs info.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1a35215..506177a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1830,8 +1830,7 @@ static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
u64 pdp = I915_READ(ring->mmio_base + offset + 4);
pdp <<= 32;
pdp |= I915_READ(ring->mmio_base + offset);
- for (i = 0; i < 4; i++)
- seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
+ seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
}
}
}
--
1.8.3.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Fix debugfs PDP register dump
2014-03-31 15:17 ` [PATCH 1/3] drm/i915: Fix debugfs PDP register dump ville.syrjala
@ 2014-04-02 17:28 ` Ben Widawsky
2014-04-03 9:26 ` Daniel Vetter
0 siblings, 1 reply; 10+ messages in thread
From: Ben Widawsky @ 2014-04-02 17:28 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Mon, Mar 31, 2014 at 06:17:16PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Iterate over all the PDP registers instead of just printing PDP0 four
> times in gen8 PPGTT debugfs info.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 1a35215..506177a 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1830,8 +1830,7 @@ static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
> u64 pdp = I915_READ(ring->mmio_base + offset + 4);
> pdp <<= 32;
> pdp |= I915_READ(ring->mmio_base + offset);
> - for (i = 0; i < 4; i++)
> - seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
> + seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
> }
> }
> }
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ben Widawsky, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Fix debugfs PDP register dump
2014-04-02 17:28 ` Ben Widawsky
@ 2014-04-03 9:26 ` Daniel Vetter
0 siblings, 0 replies; 10+ messages in thread
From: Daniel Vetter @ 2014-04-03 9:26 UTC (permalink / raw)
To: Ben Widawsky; +Cc: intel-gfx
On Wed, Apr 02, 2014 at 10:28:05AM -0700, Ben Widawsky wrote:
> On Mon, Mar 31, 2014 at 06:17:16PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Iterate over all the PDP registers instead of just printing PDP0 four
> > times in gen8 PPGTT debugfs info.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] drm/i915: Implement sema idle msg disable for all rings
2014-03-31 15:17 [PATCH 0/3] drm/i915: Gen8 workarounds and debugfs fix ville.syrjala
2014-03-31 15:17 ` [PATCH 1/3] drm/i915: Fix debugfs PDP register dump ville.syrjala
@ 2014-03-31 15:17 ` ville.syrjala
2014-03-31 17:23 ` Daniel Vetter
2014-03-31 15:17 ` [PATCH 3/3] drm/i915: Implement WaProgramMiArbOnOffAroundMiSetContext:bdw ville.syrjala
2 siblings, 1 reply; 10+ messages in thread
From: ville.syrjala @ 2014-03-31 15:17 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Previously in
commit 295e8bb73a4785b65db6655fbf6ad57c4177b551
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Thu Feb 27 21:59:01 2014 +0200
drm/i915: Disable semaphore wait event idle message on BDW
I failed to notice that all rings have their own copy of the bit that
disables the semaphore wait even idle message. So that patch only succeeded
in disabling it for the render ring. Instead we should set the bit for all
rings.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 3 ---
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 33bbaa0..84a7171 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4372,6 +4372,14 @@ static int i915_gem_init_rings(struct drm_device *dev)
goto cleanup_blt_ring;
}
+ if (IS_GEN8(dev)) {
+ struct intel_ring_buffer *ring;
+ int i;
+
+ for_each_ring(ring, dev_priv, i)
+ I915_WRITE(RING_RC_PSMI_CONTROL(ring),
+ _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
+ }
ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1f927a5..a47b4c3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1068,6 +1068,8 @@ enum punit_power_well {
#define GEN6_BLITTER_LOCK_SHIFT 16
#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
+#define RING_RC_PSMI_CONTROL(ring) ((ring)->mmio_base + 0x50)
+
#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9454a3c..21cfbc7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4876,9 +4876,6 @@ static void gen8_init_clock_gating(struct drm_device *dev)
I915_WRITE(GEN7_GT_MODE,
GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
- I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
- _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
-
/* WaDisableSDEUnitClockGating:bdw */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
--
1.8.3.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 2/3] drm/i915: Implement sema idle msg disable for all rings
2014-03-31 15:17 ` [PATCH 2/3] drm/i915: Implement sema idle msg disable for all rings ville.syrjala
@ 2014-03-31 17:23 ` Daniel Vetter
2014-03-31 18:01 ` Ville Syrjälä
0 siblings, 1 reply; 10+ messages in thread
From: Daniel Vetter @ 2014-03-31 17:23 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Mon, Mar 31, 2014 at 06:17:17PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Previously in
> commit 295e8bb73a4785b65db6655fbf6ad57c4177b551
> Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Date: Thu Feb 27 21:59:01 2014 +0200
>
> drm/i915: Disable semaphore wait event idle message on BDW
>
> I failed to notice that all rings have their own copy of the bit that
> disables the semaphore wait even idle message. So that patch only succeeded
> in disabling it for the render ring. Instead we should set the bit for all
> rings.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 3 ---
> 3 files changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 33bbaa0..84a7171 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4372,6 +4372,14 @@ static int i915_gem_init_rings(struct drm_device *dev)
> goto cleanup_blt_ring;
> }
>
> + if (IS_GEN8(dev)) {
> + struct intel_ring_buffer *ring;
> + int i;
> +
> + for_each_ring(ring, dev_priv, i)
> + I915_WRITE(RING_RC_PSMI_CONTROL(ring),
> + _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> + }
Why move this to here? Is this one of those bits which get reset on ring
init? If that's the case I think we really need to have a w/a checker to
make sure that after driver load, suspend/resume and gpu reset we always
have the same set of workarounds ...
-Daniel
>
> ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
> if (ret)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1f927a5..a47b4c3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1068,6 +1068,8 @@ enum punit_power_well {
> #define GEN6_BLITTER_LOCK_SHIFT 16
> #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
>
> +#define RING_RC_PSMI_CONTROL(ring) ((ring)->mmio_base + 0x50)
> +
> #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
> #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9454a3c..21cfbc7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4876,9 +4876,6 @@ static void gen8_init_clock_gating(struct drm_device *dev)
> I915_WRITE(GEN7_GT_MODE,
> GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
>
> - I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> - _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> -
> /* WaDisableSDEUnitClockGating:bdw */
> I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 2/3] drm/i915: Implement sema idle msg disable for all rings
2014-03-31 17:23 ` Daniel Vetter
@ 2014-03-31 18:01 ` Ville Syrjälä
0 siblings, 0 replies; 10+ messages in thread
From: Ville Syrjälä @ 2014-03-31 18:01 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Mon, Mar 31, 2014 at 07:23:20PM +0200, Daniel Vetter wrote:
> On Mon, Mar 31, 2014 at 06:17:17PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Previously in
> > commit 295e8bb73a4785b65db6655fbf6ad57c4177b551
> > Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Date: Thu Feb 27 21:59:01 2014 +0200
> >
> > drm/i915: Disable semaphore wait event idle message on BDW
> >
> > I failed to notice that all rings have their own copy of the bit that
> > disables the semaphore wait even idle message. So that patch only succeeded
> > in disabling it for the render ring. Instead we should set the bit for all
> > rings.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > drivers/gpu/drm/i915/intel_pm.c | 3 ---
> > 3 files changed, 10 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 33bbaa0..84a7171 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -4372,6 +4372,14 @@ static int i915_gem_init_rings(struct drm_device *dev)
> > goto cleanup_blt_ring;
> > }
> >
> > + if (IS_GEN8(dev)) {
> > + struct intel_ring_buffer *ring;
> > + int i;
> > +
> > + for_each_ring(ring, dev_priv, i)
> > + I915_WRITE(RING_RC_PSMI_CONTROL(ring),
> > + _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> > + }
>
> Why move this to here? Is this one of those bits which get reset on ring
> init? If that's the case I think we really need to have a w/a checker to
> make sure that after driver load, suspend/resume and gpu reset we always
> have the same set of workarounds ...
Cause I needed ring->mmio_base to be there and I couldn't be bothered to
find a better place. Now that I looked a bit, I suppose init_ring_common()
might be the right place for it. I have no idea when it gets reset.
But hold on, now that I look at the spec again it seems the bit isn't there
for the other rings after all. I must have been doubly blind when I wrote
the patch. So let's just drop it.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] drm/i915: Implement WaProgramMiArbOnOffAroundMiSetContext:bdw
2014-03-31 15:17 [PATCH 0/3] drm/i915: Gen8 workarounds and debugfs fix ville.syrjala
2014-03-31 15:17 ` [PATCH 1/3] drm/i915: Fix debugfs PDP register dump ville.syrjala
2014-03-31 15:17 ` [PATCH 2/3] drm/i915: Implement sema idle msg disable for all rings ville.syrjala
@ 2014-03-31 15:17 ` ville.syrjala
2014-04-02 4:55 ` Ben Widawsky
2 siblings, 1 reply; 10+ messages in thread
From: ville.syrjala @ 2014-03-31 15:17 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
BSpec seems to tell us we need the MI_ARB_ON_OFF w/a around
MI_SET_CONTEXT on gen8.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_context.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 746fb23..28a2b15 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -606,8 +606,8 @@ mi_set_context(struct intel_ring_buffer *ring,
if (ret)
return ret;
- /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
- if (IS_GEN7(ring->dev))
+ /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw */
+ if (INTEL_INFO(ring->dev)->gen >= 7)
intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
else
intel_ring_emit(ring, MI_NOOP);
@@ -625,7 +625,7 @@ mi_set_context(struct intel_ring_buffer *ring,
*/
intel_ring_emit(ring, MI_NOOP);
- if (IS_GEN7(ring->dev))
+ if (INTEL_INFO(ring->dev)->gen >= 7)
intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
else
intel_ring_emit(ring, MI_NOOP);
--
1.8.3.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] drm/i915: Implement WaProgramMiArbOnOffAroundMiSetContext:bdw
2014-03-31 15:17 ` [PATCH 3/3] drm/i915: Implement WaProgramMiArbOnOffAroundMiSetContext:bdw ville.syrjala
@ 2014-04-02 4:55 ` Ben Widawsky
2014-04-02 7:11 ` Daniel Vetter
0 siblings, 1 reply; 10+ messages in thread
From: Ben Widawsky @ 2014-04-02 4:55 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Mon, Mar 31, 2014 at 06:17:18PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> BSpec seems to tell us we need the MI_ARB_ON_OFF w/a around
> MI_SET_CONTEXT on gen8.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_gem_context.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 746fb23..28a2b15 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -606,8 +606,8 @@ mi_set_context(struct intel_ring_buffer *ring,
> if (ret)
> return ret;
>
> - /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
> - if (IS_GEN7(ring->dev))
> + /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw */
> + if (INTEL_INFO(ring->dev)->gen >= 7)
> intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
> else
> intel_ring_emit(ring, MI_NOOP);
> @@ -625,7 +625,7 @@ mi_set_context(struct intel_ring_buffer *ring,
> */
> intel_ring_emit(ring, MI_NOOP);
>
> - if (IS_GEN7(ring->dev))
> + if (INTEL_INFO(ring->dev)->gen >= 7)
> intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
> else
> intel_ring_emit(ring, MI_NOOP);
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ben Widawsky, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] drm/i915: Implement WaProgramMiArbOnOffAroundMiSetContext:bdw
2014-04-02 4:55 ` Ben Widawsky
@ 2014-04-02 7:11 ` Daniel Vetter
0 siblings, 0 replies; 10+ messages in thread
From: Daniel Vetter @ 2014-04-02 7:11 UTC (permalink / raw)
To: Ben Widawsky; +Cc: intel-gfx
On Tue, Apr 01, 2014 at 09:55:04PM -0700, Ben Widawsky wrote:
> On Mon, Mar 31, 2014 at 06:17:18PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > BSpec seems to tell us we need the MI_ARB_ON_OFF w/a around
> > MI_SET_CONTEXT on gen8.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 10+ messages in thread