From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH] drm/i915: Make contexts non-snooped on
 non-LLC platforms
Date: Tue, 1 Apr 2014 13:37:54 +0300
Message-ID: <20140401103754.GC21652@intel.com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
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On Tue, Apr 01, 2014 at 11:19:19AM +0100, Chris Wilson wrote:
> On Tue, Apr 01, 2014 at 01:11:02PM +0300, Ville Syrj=E4l=E4 wrote:
> > On Mon, Mar 31, 2014 at 04:39:37PM +0100, Chris Wilson wrote:
> > > On Mon, Mar 31, 2014 at 06:09:49PM +0300, ville.syrjala@linux.intel.c=
om wrote:
> > > > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > > > =

> > > > We don't do CPU access to GPU contexts so making the GPU access sno=
op
> > > > the CPU caches seems silly, and potentially expensive.
> > > > =

> > > > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > > =

> > > Maybe define a macro to be HAS_L3_CACHE?
> > =

> > What should I do with such a macro?
> =

> I am trying to express what exactly we are testing for here. It is not
> exactly LLC we care about, but L3 to hide the context switch latency.
> Even though Ben thinks that's a waste of our limited resources.

VLV has L3 too, but we can't control it via the PTEs.

-- =

Ville Syrj=E4l=E4
Intel OTC