[PATCH 21/49] drm/i915/bdw: Enable execlists in the hardware

oscar.mateo
2014-03-27T17:09:36Z

From: Ben Widawsky <benjamin.widawsky@intel.com>

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

v2: Set Replay Mode to 0 per BSpec

Michel Thierry <michel.thierry@intel.com>

v3: Several rebases.

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_lrc.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_lrc.c b/drivers/gpu/drm/i915/i915_lrc.c
index f0176ff..a726b26 100644
--- a/drivers/gpu/drm/i915/i915_lrc.c
+++ b/drivers/gpu/drm/i915/i915_lrc.c
@@ -252,7 +252,7 @@ int gen8_gem_context_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine *ring;
- int ret = -ENOSYS, ring_id;
+ int ret, ring_id;

dev_priv->hw_context_size = round_up(GEN8_LR_CONTEXT_SIZE, 4096);

@@ -265,8 +265,17 @@ int gen8_gem_context_init(struct drm_device *dev)
ring->default_context = NULL;
goto err_out;
}
+
+ I915_WRITE(RING_MODE_GEN7(ring),
+ _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
+ _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+ POSTING_READ(RING_MODE_GEN7(ring));
+
+ DRM_DEBUG_DRIVER("Enabled default logical ring context for %s\n", ring->name);
}

+ return 0;
+
err_out:
gen8_gem_context_fini(dev);
return ret;
--
1.9.0