From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH v2 3/6] drm/i915: Enabling the TLB invalidate bit in GFX Mode register Date: Wed, 2 Apr 2014 13:55:50 +0200 Message-ID: <20140402115550.GU7225@phenom.ffwll.local> References: <1395682207-7092-1-git-send-email-sourab.gupta@intel.com> <1395682207-7092-4-git-send-email-sourab.gupta@intel.com> <20140402113459.GP21652@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wi0-f178.google.com (mail-wi0-f178.google.com [209.85.212.178]) by gabe.freedesktop.org (Postfix) with ESMTP id 472396E633 for ; Wed, 2 Apr 2014 04:55:55 -0700 (PDT) Received: by mail-wi0-f178.google.com with SMTP id bs8so337078wib.5 for ; Wed, 02 Apr 2014 04:55:54 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140402113459.GP21652@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: Daniel Vetter , sourab.gupta@intel.com, Akash Goel , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 02, 2014 at 02:34:59PM +0300, Ville Syrj=E4l=E4 wrote: > On Mon, Mar 24, 2014 at 11:00:04PM +0530, sourab.gupta@intel.com wrote: > > From: Akash Goel > > = > > This patch Enables the bit for TLB invalidate in GFX Mode register > > for Gen7. > > = > > According to bspec, When enabled this bit limits the invalidation > > of the TLB only to batch buffer boundaries, to pipe_control > > commands which have the TLB invalidation bit set and sync flushes. > > If disabled, the TLB caches are flushed for every full flush of > > the pipeline. > > = > > Tested only on vlv platform. Chris has tested on ivb and hsw > > platforms. > > = > > v2: Adding the explicit enabling of this bit for all Gen7 platforms > > instead of only vlv (Chris) > > = > > Signed-off-by: Akash Goel > > Signed-off-by: Sourab Gupta > > Tested-by: Chris Wilson #ivb, hsw -Chris > = > Could I trouble you to add the w/a note? > WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw > = > No idea why it mentions only BCS and VCS, but it does seem to say that > it's essentially a new name for WaEnableFlushTlbInvalidationMode:snb. Done for both the gen6 and gen7 version of this. > = > With that: > Reviewed-by: Ville Syrj=E4l=E4 Signed-off-by: Daniel Vetter > = > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/= i915/intel_ringbuffer.c > > index bace089..eb4811a 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -617,7 +617,7 @@ static int init_render_ring(struct intel_ring_buffe= r *ring) > > = > > if (IS_GEN7(dev)) > > I915_WRITE(GFX_MODE_GEN7, > > - _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_EXPLICIT) | > > + _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | > > _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > > = > > if (INTEL_INFO(dev)->gen >=3D 5) { > > -- = > > 1.8.5.1 > = > -- = > Ville Syrj=E4l=E4 > Intel OTC -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch