From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH 1/6] drm/i915: Replace hardcoded cacheline
 size with macro
Date: Wed, 2 Apr 2014 14:57:11 -0700
Message-ID: <20140402145711.66469be9@jbarnes-desktop>
References: <1396452971-25654-1-git-send-email-chris@chris-wilson.co.uk>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from gproxy1-pub.mail.unifiedlayer.com
 (gproxy1-pub.mail.unifiedlayer.com [69.89.25.95])
 by gabe.freedesktop.org (Postfix) with SMTP id EF7EE6EC37
 for <intel-gfx@lists.freedesktop.org>; Wed,  2 Apr 2014 14:56:01 -0700 (PDT)
In-Reply-To: <1396452971-25654-1-git-send-email-chris@chris-wilson.co.uk>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Wed,  2 Apr 2014 16:36:06 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> For readibility and guess at the meaning behind the constants.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 29 ++++++++++++++++-------------
>  1 file changed, 16 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 785f246d28a8..475391ce671a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -33,6 +33,8 @@
>  #include "i915_trace.h"
>  #include "intel_drv.h"
>  
> +#define CACHELINE_BYTES 64
> +

Are you sure it's 64 on every gen?  It changes on the CPU side from
time to time... I thought it might have changed over time on the GPU
too but I haven't checked the specs.

Either way a doc ref would be nice here.

-- 
Jesse Barnes, Intel Open Source Technology Center