From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 4/7] drm/i915: Warn when DPIO read returns 0xffffffff Date: Thu, 3 Apr 2014 11:29:17 +0200 Message-ID: <20140403092917.GY7225@phenom.ffwll.local> References: <1396279290-29435-1-git-send-email-ville.syrjala@linux.intel.com> <1396279290-29435-5-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wi0-f180.google.com (mail-wi0-f180.google.com [209.85.212.180]) by gabe.freedesktop.org (Postfix) with ESMTP id 42E106EC28 for ; Thu, 3 Apr 2014 02:29:21 -0700 (PDT) Received: by mail-wi0-f180.google.com with SMTP id q5so2090846wiv.7 for ; Thu, 03 Apr 2014 02:29:20 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1396279290-29435-5-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Mar 31, 2014 at 06:21:27PM +0300, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > DPIO reads from groups/broadcast register offsets for PCS and > TX return all 1's. If that result gets used for something > we'll probably end up doing something wrong. So warn when that > happens. > = > FIXME there might be some registers where all 1's is a valid value, > so ideally we should check the register offset instead... FIXMEs like this look better in the code, I've pasted it there, too. -Daniel > = > Signed-off-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_sideband.c | 4 ++++ > 1 file changed, 4 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915= /intel_sideband.c > index 0954f13..c1e56f5 100644 > --- a/drivers/gpu/drm/i915/intel_sideband.c > +++ b/drivers/gpu/drm/i915/intel_sideband.c > @@ -182,6 +182,10 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv,= enum pipe pipe, int reg) > = > vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)= ), > DPIO_OPCODE_REG_READ, reg, &val); > + > + WARN(val =3D=3D 0xffffffff, "DPIO read pipe %c reg 0x%x =3D=3D 0x%x\n", > + pipe_name(pipe), reg, val); > + > return val; > } > = > -- = > 1.8.3.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch