From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 6/7] drm/i915: Fix framecount offset
Date: Thu, 3 Apr 2014 11:30:16 +0200
Message-ID: <20140403093016.GZ7225@phenom.ffwll.local>
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To: Jesse Barnes <jbarnes@virtuousgeek.org>
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On Wed, Apr 02, 2014 at 10:29:08AM -0700, Jesse Barnes wrote:
> On Mon, 31 Mar 2014 18:21:29 +0300
> ville.syrjala@linux.intel.com wrote:
> 
> > From: Rafael Barbalho <rafael.barbalho@intel.com>
> > 
> > The framecount register was still using the old PIPE macro instead
> > of the new PIPE2 macro
> > 
> > Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index a47b4c3..b6441da 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3623,9 +3623,9 @@ enum punit_power_well {
> >  #define   PIPE_PIXEL_MASK         0x00ffffff
> >  #define   PIPE_PIXEL_SHIFT        0
> >  /* GM45+ just has to be different */
> > -#define _PIPEA_FRMCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x70040)
> > -#define _PIPEA_FLIPCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x70044)
> > -#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
> > +#define _PIPEA_FRMCOUNT_GM45	0x70040
> > +#define _PIPEA_FLIPCOUNT_GM45	0x70044
> > +#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
> >  
> >  /* Cursor A & B regs */
> >  #define _CURACNTR		(dev_priv->info.display_mmio_offset + 0x70080)
> 
> Oh fun.
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

I've merged all the patches Jesse reviewed from this series, expect the
one Damien has a bikeshed pending.

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch