From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915/bdw: Disable idle DOP clock gating Date: Thu, 3 Apr 2014 14:00:09 +0300 Message-ID: <20140403110009.GX21652@intel.com> References: <1396493197-6622-1-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CC446E909 for ; Thu, 3 Apr 2014 04:00:22 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1396493197-6622-1-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ben Widawsky Cc: Intel GFX List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 02, 2014 at 07:46:37PM -0700, Ben Widawsky wrote: > It seems we need this at least for the current platforms we have, but > probably not later. In any event, it should cause too much harm as we do > the same thing on several other platforms. > = > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > 1 file changed, 4 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index fa00185..f73f8ca 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4868,6 +4868,10 @@ static void gen8_init_clock_gating(struct drm_devi= ce *dev) > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); > = > + /* WaDisableDopClockGating:bdw May not be needed for production */ > + I915_WRITE(GEN7_ROW_CHICKEN2, > + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); The hsd says you should also disable tcunit clock gating in GEN6_UCGCTL1. There's another w/a by the name of WaDisableRowChickenDopClockGating which seems to be the same thing (apart from the tcunit bit maybe). You might want to add that w/a note as well. > + > /* WaSwitchSolVfFArbitrationPriority:bdw */ > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); > = > -- = > 1.9.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC