From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: vlv: fix RPS interrupt mask setting Date: Thu, 3 Apr 2014 23:10:44 +0200 Message-ID: <20140403211044.GO7225@phenom.ffwll.local> References: <1396544562-5024-1-git-send-email-imre.deak@intel.com> <20140403202834.GA21064@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wi0-f181.google.com (mail-wi0-f181.google.com [209.85.212.181]) by gabe.freedesktop.org (Postfix) with ESMTP id ECAB96EA5E for ; Thu, 3 Apr 2014 14:10:47 -0700 (PDT) Received: by mail-wi0-f181.google.com with SMTP id hm4so135793wib.14 for ; Thu, 03 Apr 2014 14:10:47 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140403202834.GA21064@nuc-i3427.alporthouse.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , Imre Deak , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Apr 03, 2014 at 09:28:34PM +0100, Chris Wilson wrote: > On Thu, Apr 03, 2014 at 08:02:42PM +0300, Imre Deak wrote: > > This typo may lead to missed RPS interrupts and as a result a too > > low or too high frequency for the current workload. The interrupt mask > > will be set properly at a subsequent GPU idle event, but can get > > corrupted again at the next RPS up/down event. > > > > Signed-off-by: Imre Deak > > Embarrassing. Really odd as I thought I just cut'n'paste that line. > Reviewed-by: Chris Wilson Picked up for -fixes, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch