From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH v4 5/6] drm/i915/vlv:Implement the WA
 'WaDisable_RenderCache_OperationalFlush'
Date: Fri, 4 Apr 2014 17:59:39 +0200
Message-ID: <20140404155939.GT7225@phenom.ffwll.local>
References: <20140404111725.GA12024@intel.com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, sourab.gupta@intel.com, intel-gfx@lists.freedesktop.org, Daniel Vetter <daniel.vetter@ffwll.ch>, Ville Syrjala <ville.syrjala@linux.intel.com>, Akash Goel <akash.goel@intel.com>
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On Fri, Apr 04, 2014 at 04:24:05PM +0100, Chris Wilson wrote:
> On Fri, Apr 04, 2014 at 05:14:38PM +0530, sourab.gupta@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> > =

> > On Gen4+ platforms (except BDW), Render Cache Operational flush
> > cannot be enabled.
> > This WA is apparently required for all Gen4+ platforms,except BDW.
> > In BDW, the bit has been repurposed otherwise.
> > This has been tested only on vlv.
> > =

> > v2: Corrected the code regarding the wrong usage of
> > MASKED_BIT_DISABLE (Chris)
> > =

> > v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville)
> > =

> > v4: Adding WA for g4x, crestline, broadwater (Ville)
> > =

> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
> > Reviewed-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> =

> Note that we now have a redundant CM0_RC_OP_FLUSH_DISABLE (which fails
> the name test anyway). I'm also not a fan of
> enable(RC_OP_FLUSH_ENABLE)/disable(RC_OP_FLUSH_ENABLE) either, but as
> far as the content goes,
> =

> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> =

> Sadly, it didn't appear to fix any bugs.

Queued for -next, thanks for the patch.
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch