From mboxrd@z Thu Jan  1 00:00:00 1970
From: Damien Lespiau <damien.lespiau@intel.com>
Subject: Re: [PATCH 3/3] drm/i915/bdw: Use the GEN8 SRM when
 qeueing a flip
Date: Tue, 8 Apr 2014 07:54:28 +0100
Message-ID: <20140408065428.GN6407@strange.amr.corp.intel.com>
References: <1396898674-22510-1-git-send-email-damien.lespiau@intel.com>
 <1396898674-22510-4-git-send-email-damien.lespiau@intel.com>
 <20140407205917.GD18726@intel.com>
 <20140407222014.GL6407@strange.amr.corp.intel.com>
 <20140408062423.GM8475@nuc-i3427.alporthouse.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mga09.intel.com (mga09.intel.com [134.134.136.24])
 by gabe.freedesktop.org (Postfix) with ESMTP id 3BC6C6E88A
 for <intel-gfx@lists.freedesktop.org>; Mon,  7 Apr 2014 23:59:31 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <20140408062423.GM8475@nuc-i3427.alporthouse.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
To: Chris Wilson <chris@chris-wilson.co.uk>, Ben Widawsky <benjamin.widawsky@intel.com>, intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Tue, Apr 08, 2014 at 07:24:23AM +0100, Chris Wilson wrote:
> On Mon, Apr 07, 2014 at 11:20:14PM +0100, Damien Lespiau wrote:
> > On Mon, Apr 07, 2014 at 01:59:17PM -0700, Ben Widawsky wrote:
> > > Cool. This explains the bad DERRMR values I was seeing in in error
> > > states. I'm honestly didn't check if we actually need an SRM for BDW
> > > still, but I'll assume you did check.
> > 
> > Just checked, the LRI command still mentions that we need the SRM after
> > writes to the display engine.
> 
> It shouldn't explain the DERRMR values being incorrect though aiui. The
> SRM is to prevent system hangs from two concurrent writes, which never
> satisfied me as to how that prevents two different MMIO paths from
> accessing the same register cacheline simultaneously. Magic.

I've seen, elsewhere, this LRI not landing and DE_RRMR being the same
value as the reset value after the first flip post boot. Hence my IRC
question about the need to touch DE_RRMR if we're not waiting
explicitely for an event in the CS. This story may not end here!

-- 
Damien