From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 1/6] drm/i915: Bring UP Power Wells before disabling RC6. Date: Tue, 8 Apr 2014 15:43:32 +0300 Message-ID: <20140408124332.GH4481@intel.com> References: <1396900911-12415-1-git-send-email-rodrigo.vivi@gmail.com> <1396900911-12415-2-git-send-email-rodrigo.vivi@gmail.com> <20140407213620.GA19665@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A1686E32B for ; Tue, 8 Apr 2014 05:50:28 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140407213620.GA19665@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ben Widawsky Cc: Deepak S , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Apr 07, 2014 at 02:36:20PM -0700, Ben Widawsky wrote: > On Mon, Apr 07, 2014 at 05:01:46PM -0300, Rodrigo Vivi wrote: > > From: Deepak S > > = > > We need do forcewake before Disabling RC6, This is what the BIOS > > expects while going into suspend. > > = > > v2: updated commit message. (Daniel) > > = > > Signed-off-by: Deepak S > > Signed-off-by: Rodrigo Vivi > > --- > > drivers/gpu/drm/i915/intel_pm.c | 6 ++++++ > > 1 file changed, 6 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index 04af065..ad2ff99 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3198,8 +3198,14 @@ static void valleyview_disable_rps(struct drm_de= vice *dev) > > { > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > = > > + /* we're doing forcewake before Disabling RC6, > > + * This what the BIOS expects when going into suspend */ > > + gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > > + > > I915_WRITE(GEN6_RC_CONTROL, 0); > > = > > + gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > > + > > gen6_disable_rps_interrupts(dev); > > } > > = > = > Isn't the forcewake done as part of I915_WRITE sufficient? Writes don't do forcewake, nor is the register even part of the VLV forcewake ranges. I guess the rationale for this patche is still a bit vague. But if it's really needed, I wonder whether we should do this same dance for !VLV too? Do we have any "GPU stuck in wrong power state after suspend" type of bugs still around? -- = Ville Syrj=E4l=E4 Intel OTC