Re: [PATCH] drm/i915: Add more registers to the whitelist for mesa

From: Daniel Vetter <daniel@ffwll.ch>
To: bradley.d.volkin@intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Add more registers to the whitelist for mesa
Date: Wed, 9 Apr 2014 15:34:45 +0200	[thread overview]
Message-ID: <20140409133445.GU9262@phenom.ffwll.local> (raw)
In-Reply-To: <1396991938-6673-1-git-send-email-bradley.d.volkin@intel.com>

On Tue, Apr 08, 2014 at 02:18:58PM -0700, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
> 
> These are additional registers needed for performance monitoring and
> ARB_draw_indirect extensions in mesa.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76719
> Cc: Kenneth Graunke <kenneth@whitecape.org>
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>

Queued for -next, thanks for the patch. Ken, can you pls take a look to
make sure that this is indeed what mesa wants? I've read around in the
mesa code and Brad's patch looks sane, but I definitely lack experience in
this area.

Thanks, Daniel
> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 9 +++++++++
>  drivers/gpu/drm/i915/i915_reg.h        | 8 ++++++++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 29184d6..3486ef7 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -408,10 +408,19 @@ static const u32 gen7_render_regs[] = {
>  	REG64(PS_INVOCATION_COUNT),
>  	REG64(PS_DEPTH_COUNT),
>  	OACONTROL, /* Only allowed for LRI and SRM. See below. */
> +	GEN7_3DPRIM_START_VERTEX,
> +	GEN7_3DPRIM_VERTEX_COUNT,
> +	GEN7_3DPRIM_INSTANCE_COUNT,
> +	GEN7_3DPRIM_START_INSTANCE,
> +	GEN7_3DPRIM_BASE_VERTEX,
>  	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
>  	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
>  	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
>  	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
> +	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
> +	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
> +	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
> +	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
>  	GEN7_SO_WRITE_OFFSET(0),
>  	GEN7_SO_WRITE_OFFSET(1),
>  	GEN7_SO_WRITE_OFFSET(2),
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8e60737..533ec0a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -427,6 +427,14 @@
>  /* There are the 4 64-bit counter registers, one for each stream output */
>  #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
>  
> +#define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)
> +
> +#define GEN7_3DPRIM_START_VERTEX        0x2430
> +#define GEN7_3DPRIM_VERTEX_COUNT        0x2434
> +#define GEN7_3DPRIM_INSTANCE_COUNT      0x2438
> +#define GEN7_3DPRIM_START_INSTANCE      0x243C
> +#define GEN7_3DPRIM_BASE_VERTEX         0x2440
> +
>  #define OACONTROL 0x2360
>  
>  #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch