From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 33/71] drm/i915/chv: Fix for verifying PCBR address field. Date: Wed, 9 Apr 2014 17:57:52 +0200 Message-ID: <20140409155752.GL9262@phenom.ffwll.local> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-34-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f48.google.com (mail-ee0-f48.google.com [74.125.83.48]) by gabe.freedesktop.org (Postfix) with ESMTP id 64C266EBB5 for ; Wed, 9 Apr 2014 08:57:58 -0700 (PDT) Received: by mail-ee0-f48.google.com with SMTP id b57so2048092eek.35 for ; Wed, 09 Apr 2014 08:57:54 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1397039349-10639-34-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 09, 2014 at 01:28:31PM +0300, ville.syrjala@linux.intel.com wrote: > From: Deepak S > > This was fumbled in PCBR condition check during CHV RC6 Enable flag set > > Issue introduced in > > commit cb26b06c20094d69bcba191738960d053ac2c645 > Author: Deepak S > Date: Mon Dec 16 12:16:53 2013 +0530 > Subject: drm/i915/chv: Enable Render Standby (RC6) for Cheeryview Squash into relevant patch earlier in the series? -Daniel > > v2: Commit message change (Jani) > > v3: Mention the subject and author of the patch which introduced > the bug (Daniel) > > v4: Use VLV_PCBR_ADDR_SHIFT instead of MASK (Jani) > > v5: Commit message change. Add subject of the patch which introduced > the bug (Ville) > > Signed-off-by: Deepak S > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 5 +++-- > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e67b4a6..ac5047b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5294,6 +5294,7 @@ enum punit_power_well { > #define GEN6_GT_GFX_RC6 0x138108 > #define GEN6_GT_GFX_RC6p 0x13810C > #define GEN6_GT_GFX_RC6pp 0x138110 > +#define VLV_PCBR_ADDR_SHIFT 12 > > #define GEN6_PCODE_MAILBOX 0x138124 > #define GEN6_PCODE_READY (1<<31) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index fb533a3..acaa1cf 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3657,7 +3657,7 @@ static void cherryview_setup_pctx(struct drm_device *dev) > int pctx_size = 32*1024; > > pcbr = I915_READ(VLV_PCBR); > - if (pcbr >> 12 == 0) { > + if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { > /* > * From the Gunit register HAS: > * The Gfx driver is expected to program this register and ensure > @@ -3761,7 +3761,8 @@ static void cherryview_enable_rps(struct drm_device *dev) > DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr); > > /* 3: Enable RC6 */ > - if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE & (pcbr >> 12)) > + if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && > + (pcbr >> VLV_PCBR_ADDR_SHIFT)) > rc6_mode = GEN6_RC_CTL_EI_MODE(1) | VLV_RC_CTL_CTX_RST_PARALLEL; > > I915_WRITE(GEN6_RC_CONTROL, rc6_mode); > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch