Re: [PATCH 09/71] drm/i915/chv: Add DPINVGTT registers defines for Cherryview

Barbalho, Rafael
2014-05-01T14:09:35Z

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Wednesday, April 09, 2014 11:28 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 09/71] drm/i915/chv: Add DPINVGTT registers
> defines for Cherryview
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Due to Pipe C DPINVGTT has more bits on CHV.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 3def0fb..98f549a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3485,6 +3485,10 @@ enum punit_power_well {
> #define PLANEC_FLIPDONE_INT_EN (1<<8)
>
> #define DPINVGTT (VLV_DISPLAY_BASE +
> 0x7002c) /* VLV only */

The VLV only comment is not true anymore, it's in CHV also. With that small clean-up:
Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>

> +#define SPRITEF_INVALID_GTT_INT_EN (1<<27)
> +#define SPRITEE_INVALID_GTT_INT_EN (1<<26)
> +#define PLANEC_INVALID_GTT_INT_EN (1<<25)
> +#define CURSORC_INVALID_GTT_INT_EN (1<<24)
> #define CURSORB_INVALID_GTT_INT_EN (1<<23)
> #define CURSORA_INVALID_GTT_INT_EN (1<<22)
> #define SPRITED_INVALID_GTT_INT_EN (1<<21)
> @@ -3494,6 +3498,11 @@ enum punit_power_well {
> #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
> #define PLANEA_INVALID_GTT_INT_EN (1<<16)
> #define DPINVGTT_EN_MASK 0xff0000
> +#define DPINVGTT_EN_MASK_CHV 0xfff0000
> +#define SPRITEF_INVALID_GTT_STATUS (1<<11)
> +#define SPRITEE_INVALID_GTT_STATUS (1<<10)
> +#define PLANEC_INVALID_GTT_STATUS (1<<9)
> +#define CURSORC_INVALID_GTT_STATUS (1<<8)
> #define CURSORB_INVALID_GTT_STATUS (1<<7)
> #define CURSORA_INVALID_GTT_STATUS (1<<6)
> #define SPRITED_INVALID_GTT_STATUS (1<<5)
> @@ -3503,6 +3512,7 @@ enum punit_power_well {
> #define SPRITEA_INVALID_GTT_STATUS (1<<1)
> #define PLANEA_INVALID_GTT_STATUS (1<<0)
> #define DPINVGTT_STATUS_MASK 0xff
> +#define DPINVGTT_STATUS_MASK_CHV 0xfff
>
> #define DSPARB 0x70030
> #define DSPARB_CSTART_MASK (0x7f << 7)
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx