[PATCH 00/71] drm/i915/chv: Add Cherryview support

ville.syrjala
2014-04-09T10:29:25Z

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Cherryview (CHV) is the latest Intel(r) Atom(tm) Processor from Intel
containing Intel(r) HD Graphics.

The major GPU hardware features include:
- Gen8 Intel(r) HD Graphics graphics
- three display pipes
- three HDMI/DP/eDP display ports
- two MIPI DSI display ports
- removal of VGA support

This series exposes the basic features for CHV, bringing us to roughly
feature parity with earlier platforms.

The GT side programming follows the path laid out by Broadwell, so the
number of patches dealing with GT functionality is fairly low. By far
the largest amount of new code is added to deal with the new DP/HDMI
display PHY, and the third display pipe. The RC6 and turbo changes were
also fairly substantial.

Big thanks to everyone who contributed! In particular to Chon Ming for
the display PHY support and to Deepak for the RC6 and turbo support.

Chon Ming Lee (8):
drm/i915/chv: Add DPIO offset for Cherryview. v3
drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2
drm/i915/chv: Add vlv_pipe_to_channel
drm/i915/chv: Trigger phy common lane reset
drm/i915/chv: find the best divisor for the target clock v4
drm/i915/chv: Add update and enable pll for Cherryview
drm/i915/chv: Add phy supports for Cherryview
drm/i915/chv: Pipe select change for DP and HDMI

Damien Lespiau (1):
drm/i915/chv: Implement stolen memory size detection

Daniel Vetter (3):
drm/i915/chv: Preliminary interrupt support for Cherryview
drm/i915/chv: Add Cherryview PCI IDs
drm/i915/chv: Add early quirk for stolen

Deepak S (9):
drm/i915: Enable PM Interrupts for CHV/BDW Platform.
drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
drm/i915/chv: Added CHV specific register read and write
drm/i915/chv: Enable RPS (Turbo) for Cheeryview
drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize
sequence.
drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
drm/i915/bdw: Add BDW PM Interrupts support and BDW rps disable
drm/i915/chv: Fix for verifying PCBR address field.
drm/i915/chv: Fix for decrementing fw count in chv read/write.

Rafael Barbalho (4):
drm/i915/chv: Flush caches when programming page tables
drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHV
drm/i915/chv: Add plane C support
drm/i915/chv: Add CHV display support

Ville Syrjälä (46):
drm/i915/chv: IS_BROADWELL() should not be true for Cherryview
drm/i915/chv: Add IS_CHERRYVIEW() macro
drm/i915/chv: PPAT setup for Cherryview
drm/i915/chv: Enable aliasing PPGTT for CHV
drm/i915/chv: Add PIPESTAT register bits for Cherryview
drm/i915/chv: Add DPFLIPSTAT register bits for Cherryview
drm/i915/chv: Add display interrupt registers bits for Cherryview
drm/i915/chv: Add DPINVGTT registers defines for Cherryview
drm/i915/chv: Add Cherryview interrupt registers into debugfs
drm/i915/chv: Initial clock gating support for Cherryview
drm/i915/chv: Add DDL register defines for Cherryview
drm/i915/chv: Add DPLL state readout support
drm/i915/chv: CHV doesn't have CRT output
drm/i915/chv: Implement WaDisablePartialInstShootdown:chv
drm/i915/chv: Implement WaDisableThreadStallDopClockGating:chv
drm/i915/chv: Implement WaVSRefCountFullforceMissDisable:chv and
WaDSRefCountFullforceMissDisable:chv
drm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chv
drm/i915/chv: Implement WaDisableCSUnitClockGating:chv
drm/i915/chv: Implement WaDisableSDEUnitClockGating:chv
drm/i915/chv: Add some workaround notes
drm/i915/chv: Add a bunch of pre production workarounds
drm/i915/chv: Streamline CHV forcewake stuff
drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
drm/i915/chv: Clarify VLV/CHV PIPESTAT bits a bit more
drm/i915/chv: Use valleyview_pipestat_irq_handler() for CHV
drm/i915/chv: Make CHV irq handler loop until all interrupts are
consumed
drm/i915/chv: Configure crtc_mask correctly for CHV
drm/i915/chv: Fix gmbus for port D
drm/i915/chv: Add cursor pipe offsets
drm/i915/chv: Bump num_pipes to 3
drm/i915/chv: Fix PORT_TO_PIPE for CHV
drm/i915/chv: Register port D encoders and connectors
drm/i915/chv: Fix CHV PLL state tracking
drm/i915/chv: Move data lane deassert to encoder pre_enable
drm/i915/chv: Turn off dclkp after the PLL has been disabled
drm/i915/chv: Reset data lanes in encoder .post_disable() hook
drm/i915/chv: Set soft reset override bit for data lane resets
drm/i915/chv: Don't use PCS group access reads
drm/i915/chv: Don't do group access reads from TX lanes either
drm/i915/chv: Use RMW to toggle swing calc init
drm/i915/chv: Try to program the PHY used clock channel overrides
drm/i915/chv: Force clock buffer enables
drm/i915/chv: Force PHY clock buffers off after PLL disable
drm/i915: Don't use pipe_offset stuff for DPLL registers
drm/i915/chv: Handle video DIP registers on CHV

arch/x86/kernel/early-quirks.c | 24 +-
drivers/gpu/drm/i915/i915_debugfs.c | 51 +++-
drivers/gpu/drm/i915/i915_drv.c | 53 +++-
drivers/gpu/drm/i915/i915_drv.h | 16 +-
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 92 ++++++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 250 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 318 +++++++++++++++++++++---
drivers/gpu/drm/i915/intel_display.c | 419 ++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_dp.c | 372 +++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_drv.h | 15 ++
drivers/gpu/drm/i915/intel_hdmi.c | 234 +++++++++++++++++-
drivers/gpu/drm/i915/intel_pm.c | 331 ++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
drivers/gpu/drm/i915/intel_sideband.c | 15 ++
drivers/gpu/drm/i915/intel_uncore.c | 126 +++++++++-
include/drm/i915_pciids.h | 6 +
19 files changed, 2190 insertions(+), 138 deletions(-)

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1.8.3.2