Re: [PATCH 24/71] drm/i915/chv: Add DPLL state readout support

Imre Deak
2014-04-30T13:11:30Z

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On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add chv_crtc_clock_get() to read out the DPLL settings.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++++++++++++++++-
> 1 file changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f849c65..266d8fe 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6062,6 +6062,36 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
>
> }
>
> +static void chv_crtc_clock_get(struct intel_crtc *crtc,
> + struct intel_crtc_config *pipe_config)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + int pipe = pipe_config->cpu_transcoder;
> + enum dpio_channel port = vlv_pipe_to_channel(pipe);

'ch' would be clearer.

> + intel_clock_t clock;
> + u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
> + int refclk = 100000;
> +
> + mutex_lock(&dev_priv->dpio_lock);
> + cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
> + pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
> + pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
> + pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
> + mutex_unlock(&dev_priv->dpio_lock);
> +
> + clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
> + clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
> + clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
> + clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_SHIFT) & 0x7;
> + clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_SHIFT) & 0x1f;

We could throw in a check here for the rest of the dividers that we
assume fixed (S1, K, div_by2, div_by4).

With or without the above changes:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +
> + chv_clock(refclk, &clock);
> +
> + /* clock.dot is the fast clock */
> + pipe_config->port_clock = clock.dot / 5;
> +}
> +
> static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> struct intel_crtc_config *pipe_config)
> {
> @@ -6131,7 +6161,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> DPLL_PORTB_READY_MASK);
> }
>
> - if (IS_VALLEYVIEW(dev))
> + if (IS_CHERRYVIEW(dev))
> + chv_crtc_clock_get(crtc, pipe_config);
> + else if (IS_VALLEYVIEW(dev))
> vlv_crtc_clock_get(crtc, pipe_config);
> else
> i9xx_crtc_clock_get(crtc, pipe_config);

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