From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 66/71] drm/i915/chv: Use RMW to toggle swing calc init Date: Wed, 9 Apr 2014 18:20:33 +0200 Message-ID: <20140409162033.GS9262@phenom.ffwll.local> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-67-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f54.google.com (mail-ee0-f54.google.com [74.125.83.54]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A8866E072 for ; Wed, 9 Apr 2014 09:20:38 -0700 (PDT) Received: by mail-ee0-f54.google.com with SMTP id d49so2127362eek.27 for ; Wed, 09 Apr 2014 09:20:35 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1397039349-10639-67-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 09, 2014 at 01:29:04PM +0300, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > The spec only tells us to set individual bits here and there. So we use > RMW for most things. Do the same for the swing calc init. > = > Eventually we should optimize things to just blast the final value in > with group access whenever possible. But to do that someone needs to > take a good look at what's the reset value for each registers, and > possibly if the BIOS manages to frob with some of them. For now > use RMW access always. Usual sermon: I strongly suggest to do that transformation asap - we've alwas gotten burned in really interesting ways when relying too much on the implicit state in the hw registers ... -Daniel = > = > Signed-off-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ > drivers/gpu/drm/i915/intel_dp.c | 17 ++++++++++++++--- > drivers/gpu/drm/i915/intel_hdmi.c | 18 ++++++++++++++---- > 3 files changed, 35 insertions(+), 7 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index b91232f..7056994 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -698,6 +698,13 @@ enum punit_power_well { > #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) > #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) > = > +#define _VLV_PCS01_DW10_CH0 0x0228 > +#define _VLV_PCS23_DW10_CH0 0x0428 > +#define _VLV_PCS01_DW10_CH1 0x2628 > +#define _VLV_PCS23_DW10_CH1 0x2828 > +#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01= _DW10_CH1) > +#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23= _DW10_CH1) > + > #define _VLV_PCS_DW11_CH0 0x822c > #define _VLV_PCS_DW11_CH1 0x842c > #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel= _dp.c > index 4c54930..9cbd702 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -2346,7 +2346,13 @@ static uint32_t intel_chv_signal_levels(struct int= el_dp *intel_dp) > mutex_lock(&dev_priv->dpio_lock); > = > /* Clear calc init */ > - vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0); > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); > + val &=3D ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); > + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); > + > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); > + val &=3D ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); > + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); > = > /* Program swing deemph */ > for (i =3D 0; i < 4; i++) { > @@ -2397,8 +2403,13 @@ static uint32_t intel_chv_signal_levels(struct int= el_dp *intel_dp) > } > = > /* Start swing calculation */ > - vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), > - (DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3)); > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); > + val |=3D DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; > + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); > + > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); > + val |=3D DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; > + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); > = > /* LRC Bypass */ > val =3D vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/int= el_hdmi.c > index e912554..d2b1186 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -1283,7 +1283,13 @@ static void chv_hdmi_pre_enable(struct intel_encod= er *encoder) > /* FIXME: Fix up value only after power analysis */ > = > /* Clear calc init */ > - vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0); > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); > + val &=3D ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); > + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); > + > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); > + val &=3D ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); > + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); > = > /* FIXME: Program the support xxx V-dB */ > /* Use 800mV-0dB */ > @@ -1322,9 +1328,13 @@ static void chv_hdmi_pre_enable(struct intel_encod= er *encoder) > (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); > #endif > /* Start swing calculation */ > - vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), > - DPIO_PCS_SWING_CALC_TX0_TX2 | > - DPIO_PCS_SWING_CALC_TX1_TX3); > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); > + val |=3D DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; > + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); > + > + val =3D vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); > + val |=3D DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; > + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); > = > /* LRC Bypass */ > val =3D vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); > -- = > 1.8.3.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch