From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] tests/gen7_forcewake_mt: Don't set the GGTT
 bit in SRM command
Date: Wed, 9 Apr 2014 18:47:57 +0200
Message-ID: <20140409164757.GZ9262@phenom.ffwll.local>
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To: "Volkin, Bradley D" <bradley.d.volkin@intel.com>
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On Wed, Apr 09, 2014 at 08:12:28AM -0700, Volkin, Bradley D wrote:
> On Tue, Apr 08, 2014 at 11:20:30PM -0700, Chris Wilson wrote:
> > On Tue, Apr 08, 2014 at 02:22:16PM -0700, bradley.d.volkin@intel.com wrote:
> > > From: Brad Volkin <bradley.d.volkin@intel.com>
> > > 
> > > The command parser in newer kernels will reject it and setting this
> > > bit is not required for the actual test case.
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76670
> > > Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> > 
> > This was written how I did in the ddx...
> 
> Oh, I thought you had said that the ddx didn't use MI_STORE_REGISTER_MEM, and
> I didn't see it used in the current ddx code, so I thought that part of the
> test wasn't relevant to the actual workaround. It looked like it was just a
> write so we could see the values and check that they were updated. But if it
> is, then yeah, I don't want to change the test behavior.

Hm right I think Chris said that in the ended he never released a ddx
version with this code. Now I'm indeed rather confused what's going on. If
we don't need it I obviously prefer less complexity in the kernel cmd
parser.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch