From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 52/71] drm/i915/chv: Make CHV irq handler loop until all interrupts are consumed Date: Wed, 9 Apr 2014 19:51:37 +0300 Message-ID: <20140409165137.GS18465@intel.com> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-53-git-send-email-ville.syrjala@linux.intel.com> <20140409160501.GP9262@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 940AC6E0B0 for ; Wed, 9 Apr 2014 09:53:45 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140409160501.GP9262@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 09, 2014 at 06:05:01PM +0200, Daniel Vetter wrote: > On Wed, Apr 09, 2014 at 01:28:50PM +0300, ville.syrjala@linux.intel.com w= rote: > > From: Ville Syrj=E4l=E4 > > = > > Signed-off-by: Ville Syrj=E4l=E4 > = > Really, this is what the hw guys tell us to do? I mean we've never had a > gmch based platform which didn't need this, but I've thought with all the > gen8 irq restructuring they'd finally fix this ... This came from Rafael's observations. I was hoping re-enabling the master interrupt bit would have retriggered the CPU interrupt if any IIR bits were still high, but I guess that's not the case :( > = > /me cries > = > Cheers, Daniel > = > > --- > > drivers/gpu/drm/i915/i915_irq.c | 29 ++++++++++++++--------------- > > 1 file changed, 14 insertions(+), 15 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i91= 5_irq.c > > index 9702fde..fc9b7e6 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -1775,30 +1775,29 @@ static irqreturn_t cherryview_irq_handler(int i= rq, void *arg) > > u32 master_ctl, iir; > > irqreturn_t ret =3D IRQ_NONE; > > = > > - master_ctl =3D I915_READ(GEN8_MASTER_IRQ) & ~DE_MASTER_IRQ_CONTROL; > > - iir =3D I915_READ(VLV_IIR); > > + for (;;) { > > + master_ctl =3D I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; > > + iir =3D I915_READ(VLV_IIR); > > = > > - if (master_ctl =3D=3D 0 && iir =3D=3D 0) > > - return IRQ_NONE; > > + if (master_ctl =3D=3D 0 && iir =3D=3D 0) > > + break; > > = > > - I915_WRITE(GEN8_MASTER_IRQ, 0); > > + I915_WRITE(GEN8_MASTER_IRQ, 0); > > = > > - gen8_gt_irq_handler(dev, dev_priv, master_ctl); > > + gen8_gt_irq_handler(dev, dev_priv, master_ctl); > > = > > - valleyview_pipestat_irq_handler(dev, iir); > > + valleyview_pipestat_irq_handler(dev, iir); > > = > > - /* Consume port. Then clear IIR or we'll miss events */ > > - if (iir & I915_DISPLAY_PORT_INTERRUPT) { > > + /* Consume port. Then clear IIR or we'll miss events */ > > i9xx_hpd_irq_handler(dev, iir); > > - ret =3D IRQ_HANDLED; > > - } > > = > > - I915_WRITE(VLV_IIR, iir); > > + I915_WRITE(VLV_IIR, iir); > > = > > - I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); > > - POSTING_READ(GEN8_MASTER_IRQ); > > + I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); > > + POSTING_READ(GEN8_MASTER_IRQ); > > = > > - ret =3D IRQ_HANDLED; > > + ret =3D IRQ_HANDLED; > > + } > > = > > return ret; > > } > > -- = > > 1.8.3.2 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- = Ville Syrj=E4l=E4 Intel OTC