From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 44/71] drm/i915/chv: Fix for decrementing fw count in chv read/write. Date: Wed, 9 Apr 2014 20:49:55 +0300 Message-ID: <20140409174955.GV18465@intel.com> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-45-git-send-email-ville.syrjala@linux.intel.com> <20140409155921.GM9262@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id AB4526EB83 for ; Wed, 9 Apr 2014 10:50:56 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140409155921.GM9262@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 09, 2014 at 05:59:21PM +0200, Daniel Vetter wrote: > On Wed, Apr 09, 2014 at 01:28:42PM +0300, ville.syrjala@linux.intel.com w= rote: > > From: Deepak S > > = > > This was fumbled in chv specific forcewake count during mmio reg read/w= rite. > > = > > Issue introduced in > > = > > commit 95cf8b69f647322048929baffa8c7865aa6df2ad > > Author: Deepak S > > Date: Mon Dec 16 12:16:54 2013 +0530 > > Subject: drm/i915/chv: Added CHV specific register read and write > = > Again please squash in as a fixup. Oh there was this patch too that touches the forcewake. Yeah this should definitely be squashed. > -Daniel > = > > = > > Signed-off-by: Deepak S > > --- > > drivers/gpu/drm/i915/intel_uncore.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915= /intel_uncore.c > > index 8e3c686..ccad770 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -638,12 +638,12 @@ chv_read##x(struct drm_i915_private *dev_priv, of= f_t reg, bool trace) { \ > > } \ > > val =3D __raw_i915_read##x(dev_priv, reg); \ > > if (FORCEWAKE_RENDER & fwengine) { \ > > - if (dev_priv->uncore.fw_rendercount++ =3D=3D 0) \ > > + if (--dev_priv->uncore.fw_rendercount =3D=3D 0) \ > > (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ > > fwengine); \ > > } \ > > if (FORCEWAKE_MEDIA & fwengine) { \ > > - if (dev_priv->uncore.fw_mediacount++ =3D=3D 0) \ > > + if (--dev_priv->uncore.fw_mediacount =3D=3D 0) \ > > (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ > > fwengine); \ > > } \ > > @@ -803,12 +803,12 @@ chv_write##x(struct drm_i915_private *dev_priv, o= ff_t reg, u##x val, bool trace) > > } \ > > __raw_i915_write##x(dev_priv, reg, val); \ > > if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \ > > - if (dev_priv->uncore.fw_rendercount++ =3D=3D 0) \ > > + if (--dev_priv->uncore.fw_rendercount =3D=3D 0) \ > > (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ > > fwengine); \ > > } \ > > if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \ > > - if (dev_priv->uncore.fw_mediacount++ =3D=3D 0) \ > > + if (--dev_priv->uncore.fw_mediacount =3D=3D 0) \ > > (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ > > fwengine); \ > > } \ > > -- = > > 1.8.3.2 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- = Ville Syrj=E4l=E4 Intel OTC