From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] SQUASH: drm/i915: One more register for mesa Date: Wed, 9 Apr 2014 21:54:46 +0200 Message-ID: <20140409195446.GD9262@phenom.ffwll.local> References: <20140409164644.GY9262@phenom.ffwll.local> <1397063574-10928-1-git-send-email-bradley.d.volkin@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f43.google.com (mail-ee0-f43.google.com [74.125.83.43]) by gabe.freedesktop.org (Postfix) with ESMTP id B1B646E029 for ; Wed, 9 Apr 2014 12:54:50 -0700 (PDT) Received: by mail-ee0-f43.google.com with SMTP id e53so2281962eek.30 for ; Wed, 09 Apr 2014 12:54:49 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1397063574-10928-1-git-send-email-bradley.d.volkin@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: bradley.d.volkin@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 09, 2014 at 10:12:54AM -0700, bradley.d.volkin@intel.com wrote: > From: Brad Volkin > > Originally left out because it wasn't used. But it may be needed > and doesn't pose any risk, so add to the whitelist. > > Signed-off-by: Brad Volkin Fixup squashed in, thanks. -Daniel > --- > drivers/gpu/drm/i915/i915_cmd_parser.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c > index 3486ef7..9bac097 100644 > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c > @@ -408,6 +408,7 @@ static const u32 gen7_render_regs[] = { > REG64(PS_INVOCATION_COUNT), > REG64(PS_DEPTH_COUNT), > OACONTROL, /* Only allowed for LRI and SRM. See below. */ > + GEN7_3DPRIM_END_OFFSET, > GEN7_3DPRIM_START_VERTEX, > GEN7_3DPRIM_VERTEX_COUNT, > GEN7_3DPRIM_INSTANCE_COUNT, > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index f49569b..46ea233 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -430,6 +430,7 @@ > > #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8) > > +#define GEN7_3DPRIM_END_OFFSET 0x2420 > #define GEN7_3DPRIM_START_VERTEX 0x2430 > #define GEN7_3DPRIM_VERTEX_COUNT 0x2434 > #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438 > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch