From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence. Date: Thu, 10 Apr 2014 09:00:03 +0200 Message-ID: <20140410070003.GJ9262@phenom.ffwll.local> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-31-git-send-email-ville.syrjala@linux.intel.com> <20140409130654.GA4573@nuc-i3427.alporthouse.com> <53459CAD.9060102@linux.intel.com> <20140409223304.GA4425@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f54.google.com (mail-ee0-f54.google.com [74.125.83.54]) by gabe.freedesktop.org (Postfix) with ESMTP id E2EF56E18F for ; Thu, 10 Apr 2014 00:00:06 -0700 (PDT) Received: by mail-ee0-f54.google.com with SMTP id d49so2672901eek.27 for ; Thu, 10 Apr 2014 00:00:05 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140409223304.GA4425@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 09, 2014 at 03:33:04PM -0700, Ben Widawsky wrote: > On Thu, Apr 10, 2014 at 12:47:01AM +0530, Deepak S wrote: > > > > On Wednesday 09 April 2014 06:36 PM, Chris Wilson wrote: > > >On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrjala@linux.intel.com wrote: > > >>+static void gen8_enable_rps_interrupts(struct drm_device *dev) > > >>+{ > > >>+ struct drm_i915_private *dev_priv = dev->dev_private; > > >>+ > > >>+ /* Clear out any stale interrupts first */ > > >>+ spin_lock_irq(&dev_priv->irq_lock); > > >>+ WARN_ON(dev_priv->rps.pm_iir); > > >>+ I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2))); > > >>+ dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS; > > >>+ I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask); > > >>+ spin_unlock_irq(&dev_priv->irq_lock); > > >>+ > > >>+ I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS); > > >>+ /* only unmask PM interrupts we need. Mask all others. */ > > >>+ I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS); > > >PMINTRMSK handling is now a part of set_rps (and so this line is > > >redundant). > > >-Chris > > > > Thanks Chris. I will make the changes based on the current nightly code > > > > > > I think my patch kept up with this, but I too am not sure. In either > case feel free to reuse, copy, or review that one. > > I don't think I've mailed out the very latest version, but I am pretty > sure I mailed out after the last painful rebase (and it's tested on > BDW). > > http://cgit.freedesktop.org/~bwidawsk/drm-intel/commit/?h=bdw-rc6&id=80fbe001fc4ba38c41db3cec177c9157b2613c3c Oh right we have some duplication in the gen8 rps/rc6 support story and never worked that out while the patches where still in internal. Deepak/Ben can you pls sort this out? Imo best if we just combine the patches so that we have one series for both bdw and chv, tested on both ofc. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch