From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH] Revert "drm/i915: fix infinite loop at gen6_update_ring_freq" Date: Thu, 10 Apr 2014 10:50:43 -0700 Message-ID: <20140410175043.GB7294@bwidawsk.net> References: <1397113487-25717-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail.bwidawsk.net (bwidawsk.net [166.78.191.112]) by gabe.freedesktop.org (Postfix) with ESMTP id 92EC36EC78 for ; Thu, 10 Apr 2014 10:50:57 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1397113487-25717-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: Intel Graphics Development , Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Thu, Apr 10, 2014 at 09:04:47AM +0200, Daniel Vetter wrote: > This reverts commit 4b28a1f3ef55a3b0b68dbab1fe6dbaf18e186710. > > This patch duct-tapes over some issue in the current bdw rps patches > which must wait with enabling rc6/rps until the very first batch has > been submitted by userspace. > > But those patches aren't merged yet, and for upstream we need to have > an in-kernel emission of the very first batch. I shouldn't have > merged this patch so let's revert it again. I said this on the mailing last before you merged the patch. > > Also Imre noticed that even when rps is set up normally there's a > small window (due to the 1s delay of the async rps init work) where we > could runtime suspend already and blow up all over the place. Imre has > a proper fix to block runtime pm until the rps init work has > successfully completed. > > Cc: Paulo Zanoni > Cc: Imre Deak > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/intel_pm.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 8531cf6e2774..dc7adadbb945 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3522,8 +3522,7 @@ void gen6_update_ring_freq(struct drm_device *dev) > * to use for memory access. We do this by specifying the IA frequency > * the PCU should use as a reference to determine the ring frequency. > */ > - for (gpu_freq = dev_priv->rps.max_freq_softlimit; > - gpu_freq >= dev_priv->rps.min_freq_softlimit && gpu_freq != 0; > + for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit; > gpu_freq--) { > int diff = dev_priv->rps.max_freq_softlimit - gpu_freq; > unsigned int ia_freq = 0, ring_freq = 0; > -- > 1.8.5.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ben Widawsky, Intel Open Source Technology Center