[PATCH] drm/i915/bdw: cs-stall before state cache invld w/a

[PATCH] drm/i915/bdw: cs-stall before state cache invld w/a

[Ben Widawsky]

We do this already for previous GENs. I guess we must do it for BDW too
according to DOCS.

"Pipe_control with CS-stall bit set must be issued before a
pipe-control command that has the State Cache Invalidate bit set."

This does not solve the problem I have unfortunately.

I didn't check if this was in Ville's CHV series. If it was, I
apologize.

NOTE: I tried to use smaller lengths for the command, but nothing made
it happy except 6.

Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Jordan Justen <jljusten@gmail.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a9b04d1..092dea0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -266,17 +266,25 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
 static int
 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 {
-	int ret;
+	int ret, size = 4;
 
-	ret = intel_ring_begin(ring, 4);
+	if (IS_BROADWELL(ring->dev))
+		size += 2;
+
+	ret = intel_ring_begin(ring, size);
 	if (ret)
 		return ret;
 
-	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
+	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(size));
 	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 			      PIPE_CONTROL_STALL_AT_SCOREBOARD);
 	intel_ring_emit(ring, 0);
 	intel_ring_emit(ring, 0);
+	if (IS_BROADWELL(ring->dev)) {
+		intel_ring_emit(ring, 0);
+		intel_ring_emit(ring, 0);
+	}
+
 	intel_ring_advance(ring);
 
 	return 0;
@@ -389,6 +397,11 @@ gen8_render_ring_flush(struct intel_ring_buffer *ring,
 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_QW_WRITE;
 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+
+		/* Workaround: we must issue a pipe_control with CS-stall bit
+		 * set before a pipe_control command that has the state cache
+		 * invalidate bit set. */
+		gen7_render_ring_cs_stall_wa(ring);
 	}
 
 	ret = intel_ring_begin(ring, 6);
-- 
1.9.1

Re: [PATCH] drm/i915/bdw: cs-stall before state cache invld w/a

[Ville Syrjälä]

On Fri, Apr 11, 2014 at 06:46:08PM -0700, Ben Widawsky wrote:
> We do this already for previous GENs. I guess we must do it for BDW too
> according to DOCS.
> 
> "Pipe_control with CS-stall bit set must be issued before a
> pipe-control command that has the State Cache Invalidate bit set."
> 
> This does not solve the problem I have unfortunately.
> 
> I didn't check if this was in Ville's CHV series. If it was, I
> apologize.

No, but it was posted by Ken some time ago already. I picked up Ken's
patches and was going to repost them as part of my next workarounds
series.

> 
> NOTE: I tried to use smaller lengths for the command, but nothing made
> it happy except 6.
> 
> Cc: Kenneth Graunke <kenneth@whitecape.org>
> Cc: Jordan Justen <jljusten@gmail.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++++++++++++++++---
>  1 file changed, 16 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index a9b04d1..092dea0 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -266,17 +266,25 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
>  static int
>  gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
>  {
> -	int ret;
> +	int ret, size = 4;
>  
> -	ret = intel_ring_begin(ring, 4);
> +	if (IS_BROADWELL(ring->dev))
> +		size += 2;
> +
> +	ret = intel_ring_begin(ring, size);
>  	if (ret)
>  		return ret;
>  
> -	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
> +	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(size));
>  	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
>  			      PIPE_CONTROL_STALL_AT_SCOREBOARD);
>  	intel_ring_emit(ring, 0);
>  	intel_ring_emit(ring, 0);
> +	if (IS_BROADWELL(ring->dev)) {
> +		intel_ring_emit(ring, 0);
> +		intel_ring_emit(ring, 0);
> +	}
> +
>  	intel_ring_advance(ring);
>  
>  	return 0;
> @@ -389,6 +397,11 @@ gen8_render_ring_flush(struct intel_ring_buffer *ring,
>  		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
>  		flags |= PIPE_CONTROL_QW_WRITE;
>  		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> +
> +		/* Workaround: we must issue a pipe_control with CS-stall bit
> +		 * set before a pipe_control command that has the state cache
> +		 * invalidate bit set. */
> +		gen7_render_ring_cs_stall_wa(ring);
>  	}
>  
>  	ret = intel_ring_begin(ring, 6);
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC