From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915/bdw: cs-stall before state cache invld w/a Date: Sat, 12 Apr 2014 11:46:02 +0300 Message-ID: <20140412084601.GJ18465@intel.com> References: <1397267168-21743-1-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id D26CF6E4F0 for ; Sat, 12 Apr 2014 01:46:05 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1397267168-21743-1-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ben Widawsky Cc: Intel GFX List-Id: intel-gfx@lists.freedesktop.org On Fri, Apr 11, 2014 at 06:46:08PM -0700, Ben Widawsky wrote: > We do this already for previous GENs. I guess we must do it for BDW too > according to DOCS. > = > "Pipe_control with CS-stall bit set must be issued before a > pipe-control command that has the State Cache Invalidate bit set." > = > This does not solve the problem I have unfortunately. > = > I didn't check if this was in Ville's CHV series. If it was, I > apologize. No, but it was posted by Ken some time ago already. I picked up Ken's patches and was going to repost them as part of my next workarounds series. > = > NOTE: I tried to use smaller lengths for the command, but nothing made > it happy except 6. > = > Cc: Kenneth Graunke > Cc: Jordan Justen > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index a9b04d1..092dea0 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -266,17 +266,25 @@ gen6_render_ring_flush(struct intel_ring_buffer *ri= ng, > static int > gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) > { > - int ret; > + int ret, size =3D 4; > = > - ret =3D intel_ring_begin(ring, 4); > + if (IS_BROADWELL(ring->dev)) > + size +=3D 2; > + > + ret =3D intel_ring_begin(ring, size); > if (ret) > return ret; > = > - intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); > + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(size)); > intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | > PIPE_CONTROL_STALL_AT_SCOREBOARD); > intel_ring_emit(ring, 0); > intel_ring_emit(ring, 0); > + if (IS_BROADWELL(ring->dev)) { > + intel_ring_emit(ring, 0); > + intel_ring_emit(ring, 0); > + } > + > intel_ring_advance(ring); > = > return 0; > @@ -389,6 +397,11 @@ gen8_render_ring_flush(struct intel_ring_buffer *rin= g, > flags |=3D PIPE_CONTROL_STATE_CACHE_INVALIDATE; > flags |=3D PIPE_CONTROL_QW_WRITE; > flags |=3D PIPE_CONTROL_GLOBAL_GTT_IVB; > + > + /* Workaround: we must issue a pipe_control with CS-stall bit > + * set before a pipe_control command that has the state cache > + * invalidate bit set. */ > + gen7_render_ring_cs_stall_wa(ring); > } > = > ret =3D intel_ring_begin(ring, 6); > -- = > 1.9.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC