* [PATCH 1/2] drm/i915: Don't set the 8to6 dither flag when not scaling
@ 2014-01-27 9:00 Daniel Vetter
2014-01-27 9:00 ` [PATCH 2/2] drm/i915: read lvds_border_bits state from encoder->get_config Daniel Vetter
2014-04-13 9:52 ` [PATCH 1/2] drm/i915: Don't set the 8to6 dither flag when not scaling Daniel Vetter
0 siblings, 2 replies; 5+ messages in thread
From: Daniel Vetter @ 2014-01-27 9:00 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Apparently we really only need this when the pfit is enabled, at least
I couldn't dicern any difference here. Furthermore the hacks we have
to reconstruct this bit is a bit glaring, and probably only works
because we can't move the lvds port to any other pipe than pipe B on
gen2/3.
So let's just rip this out.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_lvds.c | 7 -------
drivers/gpu/drm/i915/intel_panel.c | 8 ++++----
2 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 8bcb93a2a9f6..8a3ebe940a74 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -111,13 +111,6 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
pipe_config->adjusted_mode.flags |= flags;
- /* gen2/3 store dither state in pfit control, needs to match */
- if (INTEL_INFO(dev)->gen < 4) {
- tmp = I915_READ(PFIT_CONTROL);
-
- pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
- }
-
dotclock = pipe_config->port_clock;
if (HAS_PCH_SPLIT(dev_priv->dev))
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 9f83ab06fb5e..41116753f1c0 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -308,16 +308,16 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
PFIT_FILTER_FUZZY);
+ /* Make sure pre-965 set dither correctly for 18bpp panels. */
+ if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
+ pfit_control |= PANEL_8TO6_DITHER_ENABLE;
+
out:
if ((pfit_control & PFIT_ENABLE) == 0) {
pfit_control = 0;
pfit_pgm_ratios = 0;
}
- /* Make sure pre-965 set dither correctly for 18bpp panels. */
- if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
- pfit_control |= PANEL_8TO6_DITHER_ENABLE;
-
pipe_config->gmch_pfit.control = pfit_control;
pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
pipe_config->gmch_pfit.lvds_border_bits = border;
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/i915: read lvds_border_bits state from encoder->get_config
2014-01-27 9:00 [PATCH 1/2] drm/i915: Don't set the 8to6 dither flag when not scaling Daniel Vetter
@ 2014-01-27 9:00 ` Daniel Vetter
2014-01-27 9:57 ` [Intel-gfx] " Chris Wilson
2014-04-13 9:52 ` [PATCH 1/2] drm/i915: Don't set the 8to6 dither flag when not scaling Daniel Vetter
1 sibling, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2014-01-27 9:00 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter, Alan Stern, stable
We seem to get confused when trying to reconstruct this from the pipe
get_config when reading out pfit state. In our code these two are
connected, but in the hardware they're not.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74081
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 3 ---
drivers/gpu/drm/i915/intel_lvds.c | 4 ++++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 65b470baee39..18e76d9e2248 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5478,9 +5478,6 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
pipe_config->gmch_pfit.control = tmp;
pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
- if (INTEL_INFO(dev)->gen < 5)
- pipe_config->gmch_pfit.lvds_border_bits =
- I915_READ(LVDS) & LVDS_BORDER_ENABLE;
}
static void vlv_crtc_clock_get(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 8a3ebe940a74..772b5d62d54b 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -117,6 +117,10 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
ironlake_check_encoder_dotclock(pipe_config, dotclock);
pipe_config->adjusted_mode.crtc_clock = dotclock;
+
+ if (INTEL_INFO(dev)->gen < 5)
+ pipe_config->gmch_pfit.lvds_border_bits =
+ tmp & LVDS_BORDER_ENABLE;
}
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
--
1.8.4.rc3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: read lvds_border_bits state from encoder->get_config
2014-01-27 9:00 ` [PATCH 2/2] drm/i915: read lvds_border_bits state from encoder->get_config Daniel Vetter
@ 2014-01-27 9:57 ` Chris Wilson
2014-01-27 10:18 ` Daniel Vetter
0 siblings, 1 reply; 5+ messages in thread
From: Chris Wilson @ 2014-01-27 9:57 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development, Alan Stern, stable
On Mon, Jan 27, 2014 at 10:00:31AM +0100, Daniel Vetter wrote:
> We seem to get confused when trying to reconstruct this from the pipe
> get_config when reading out pfit state. In our code these two are
> connected, but in the hardware they're not.
Huh? I think the change is to only read out the border-enable bit when
LVDS is enabled. But that is only a guess at what your intent is here.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: read lvds_border_bits state from encoder->get_config
2014-01-27 9:57 ` [Intel-gfx] " Chris Wilson
@ 2014-01-27 10:18 ` Daniel Vetter
0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2014-01-27 10:18 UTC (permalink / raw)
To: Chris Wilson, Daniel Vetter, Intel Graphics Development,
Alan Stern, stable
On Mon, Jan 27, 2014 at 09:57:11AM +0000, Chris Wilson wrote:
> On Mon, Jan 27, 2014 at 10:00:31AM +0100, Daniel Vetter wrote:
> > We seem to get confused when trying to reconstruct this from the pipe
> > get_config when reading out pfit state. In our code these two are
> > connected, but in the hardware they're not.
>
> Huh? I think the change is to only read out the border-enable bit when
> LVDS is enabled. But that is only a guess at what your intent is here.
Yeah, that's the idea. The encoder specific get_config is only called if
get_hw_state indicates that the encoder is on. Since we always reset the
lvds border bits in the lvds->mode_set callback to the one in the pipe
config this should fix the mismatch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/i915: Don't set the 8to6 dither flag when not scaling
2014-01-27 9:00 [PATCH 1/2] drm/i915: Don't set the 8to6 dither flag when not scaling Daniel Vetter
2014-01-27 9:00 ` [PATCH 2/2] drm/i915: read lvds_border_bits state from encoder->get_config Daniel Vetter
@ 2014-04-13 9:52 ` Daniel Vetter
1 sibling, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2014-04-13 9:52 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
On Mon, Jan 27, 2014 at 10:00:30AM +0100, Daniel Vetter wrote:
> Apparently we really only need this when the pfit is enabled, at least
> I couldn't dicern any difference here. Furthermore the hacks we have
> to reconstruct this bit is a bit glaring, and probably only works
> because we can't move the lvds port to any other pipe than pipe B on
> gen2/3.
>
> So let's just rip this out.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
I've just written this exact patch again, so figured I might as well merge
it. r-b still appreciated ...
-Daniel
> ---
> drivers/gpu/drm/i915/intel_lvds.c | 7 -------
> drivers/gpu/drm/i915/intel_panel.c | 8 ++++----
> 2 files changed, 4 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 8bcb93a2a9f6..8a3ebe940a74 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -111,13 +111,6 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
>
> pipe_config->adjusted_mode.flags |= flags;
>
> - /* gen2/3 store dither state in pfit control, needs to match */
> - if (INTEL_INFO(dev)->gen < 4) {
> - tmp = I915_READ(PFIT_CONTROL);
> -
> - pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
> - }
> -
> dotclock = pipe_config->port_clock;
>
> if (HAS_PCH_SPLIT(dev_priv->dev))
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 9f83ab06fb5e..41116753f1c0 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -308,16 +308,16 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
> pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
> PFIT_FILTER_FUZZY);
>
> + /* Make sure pre-965 set dither correctly for 18bpp panels. */
> + if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
> + pfit_control |= PANEL_8TO6_DITHER_ENABLE;
> +
> out:
> if ((pfit_control & PFIT_ENABLE) == 0) {
> pfit_control = 0;
> pfit_pgm_ratios = 0;
> }
>
> - /* Make sure pre-965 set dither correctly for 18bpp panels. */
> - if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
> - pfit_control |= PANEL_8TO6_DITHER_ENABLE;
> -
> pipe_config->gmch_pfit.control = pfit_control;
> pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
> pipe_config->gmch_pfit.lvds_border_bits = border;
> --
> 1.8.4.rc3
>
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2014-04-13 9:52 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2014-01-27 9:00 [PATCH 1/2] drm/i915: Don't set the 8to6 dither flag when not scaling Daniel Vetter
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2014-01-27 9:57 ` [Intel-gfx] " Chris Wilson
2014-01-27 10:18 ` Daniel Vetter
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