From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 2/2] drm/i915: Enable PM Interrupts target via Display Interface. Date: Mon, 14 Apr 2014 22:36:55 +0300 Message-ID: <20140414193655.GO18465@intel.com> References: <1397495475-22667-1-git-send-email-deepak.s@intel.com> <1397495475-22667-3-git-send-email-deepak.s@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 262706E0FC for ; Mon, 14 Apr 2014 12:37:16 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1397495475-22667-3-git-send-email-deepak.s@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: deepak.s@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Apr 14, 2014 at 10:41:15PM +0530, deepak.s@intel.com wrote: > From: Deepak S > = > In BDW, Apart from unmasking up/down threshold interrupts. we need > to umask bit 32 of PM_INTRMASK to route interrupts to target via Display > Interface. > = > Signed-off-by: Deepak S > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 2 ++ > 2 files changed, 3 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index c2dd436..8c7841b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5105,6 +5105,7 @@ enum punit_power_well { > #define GEN6_RC6p_THRESHOLD 0xA0BC > #define GEN6_RC6pp_THRESHOLD 0xA0C0 > #define GEN6_PMINTRMSK 0xA168 > +#define GEN8_PMINTR_REDIRECT_TO_NON_DISP 0x7FFFFFFF Defining is as (1<<31) would make more sense to me. > = > #define GEN6_PMISR 0x44020 > #define GEN6_PMIMR 0x44024 /* rps_lock */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 27b64ab..6b123cd 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3066,6 +3066,8 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private= *dev_priv, u8 val) > if (INTEL_INFO(dev_priv->dev)->gen <=3D 7 && !IS_HASWELL(dev_priv->dev)) > mask |=3D GEN6_PM_RP_UP_EI_EXPIRED; > = > + mask &=3D GEN8_PMINTR_REDIRECT_TO_NON_DISP; > + > return ~mask; > } > = > -- = > 1.8.5.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC