Re: [PATCH 2/2] drm/i915: Enable PM Interrupts target via Display Interface.

Ville Syrjälä
2014-04-16T13:32:24Z

On Mon, Apr 14, 2014 at 10:36:55PM +0300, Ville Syrjälä wrote:
> On Mon, Apr 14, 2014 at 10:41:15PM +0530, deepak.s@intel.com wrote:
> > From: Deepak S <deepak.s@intel.com>
> >
> > In BDW, Apart from unmasking up/down threshold interrupts. we need
> > to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
> > Interface.
> >
> > Signed-off-by: Deepak S <deepak.s@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 2 ++
> > 2 files changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c2dd436..8c7841b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5105,6 +5105,7 @@ enum punit_power_well {
> > #define GEN6_RC6p_THRESHOLD 0xA0BC
> > #define GEN6_RC6pp_THRESHOLD 0xA0C0
> > #define GEN6_PMINTRMSK 0xA168
> > +#define GEN8_PMINTR_REDIRECT_TO_NON_DISP 0x7FFFFFFF
>
> Defining is as (1<<31) would make more sense to me.
>
> >
> > #define GEN6_PMISR 0x44020
> > #define GEN6_PMIMR 0x44024 /* rps_lock */
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 27b64ab..6b123cd 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3066,6 +3066,8 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
> > if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
> > mask |= GEN6_PM_RP_UP_EI_EXPIRED;
> >
> > + mask &= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
> > +
> > return ~mask;

Oh and just noticed this doesn't actually do anything.
& must come after ~ to get the expected result.

> > }
> >
> > --
> > 1.8.5.2
> >
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> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC

--
Ville Syrjälä
Intel OTC