From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 1/2] drm/i915: Don't vblank wait on ilk-ivb after pipe enable Date: Tue, 15 Apr 2014 23:35:01 +0300 Message-ID: <20140415203501.GA18465@intel.com> References: <1397580083-11558-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 323636E2E9 for ; Tue, 15 Apr 2014 13:35:05 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1397580083-11558-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Tue, Apr 15, 2014 at 06:41:22PM +0200, Daniel Vetter wrote: > Like on hsw/bdw the pipe isn't actually running yet at this point. > This holds for both pch ports and the cpu edp port according to my > testing on ilk, snb and ivb. > = > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=3D77297 > Signed-off-by: Daniel Vetter Yeah I hate these weird waits we have sprinkled all over the place w/o clear justification. Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_display.c | 14 ++++---------- > 1 file changed, 4 insertions(+), 10 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 1aae7361b7a5..e0310e3018ee 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1827,16 +1827,6 @@ static void intel_enable_pipe(struct intel_crtc *c= rtc) > = > I915_WRITE(reg, val | PIPECONF_ENABLE); > POSTING_READ(reg); > - > - /* > - * There's no guarantee the pipe will really start running now. It > - * depends on the Gen, the output type and the relative order between > - * pipe and plane enabling. Avoid waiting on HSW+ since it's not > - * necessary. > - * TODO: audit the previous gens. > - */ > - if (INTEL_INFO(dev)->gen <=3D 7 && !IS_HASWELL(dev)) > - intel_wait_for_vblank(dev_priv->dev, pipe); > } > = > /** > @@ -4461,7 +4451,9 @@ static void valleyview_crtc_enable(struct drm_crtc = *crtc) > = > intel_update_watermarks(crtc); > intel_enable_pipe(intel_crtc); > + intel_wait_for_vblank(dev_priv->dev, pipe); > intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); > + > intel_enable_primary_hw_plane(dev_priv, plane, pipe); > intel_enable_planes(crtc); > intel_crtc_update_cursor(crtc, true); > @@ -4546,7 +4538,9 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) > = > intel_update_watermarks(crtc); > intel_enable_pipe(intel_crtc); > + intel_wait_for_vblank(dev_priv->dev, pipe); > intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); > + > intel_enable_primary_hw_plane(dev_priv, plane, pipe); > intel_enable_planes(crtc); > /* The fixup needs to happen before cursor is enabled */ > -- = > 1.8.4.rc3 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC