From: Jeff McGee <jeff.mcgee@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org, Ben Widawsky <ben@bwidawsk.net>,
Ben Widawsky <benjamin.widawsky@intel.com>
Subject: Re: [PATCH 19/49] drm/i915/bdw: Populate LR contexts (somewhat)
Date: Tue, 15 Apr 2014 17:32:46 -0500 [thread overview]
Message-ID: <20140415223245.GD16015@jeffdesk> (raw)
In-Reply-To: <20140415210802.GB10722@phenom.ffwll.local>
On Tue, Apr 15, 2014 at 11:08:02PM +0200, Daniel Vetter wrote:
> On Tue, Apr 15, 2014 at 03:43:23PM -0500, Jeff McGee wrote:
> > On Tue, Apr 15, 2014 at 11:10:34AM -0500, Jeff McGee wrote:
> > > On Tue, Apr 15, 2014 at 11:00:33AM -0500, Jeff McGee wrote:
> > > > On Thu, Mar 27, 2014 at 05:59:48PM +0000, oscar.mateo@intel.com wrote:
> > > > > From: Ben Widawsky <benjamin.widawsky@intel.com>
> > > > >
> > > > > For the most part, logical rinf context objects are similar to hardware
> > > > > contexts in that the backing object is meant to be opaque. There are
> > > > > some exceptions where we need to poke certain offsets of the object for
> > > > > initialization, updating the tail pointer or updating the PDPs.
> > > > >
> > > > > For our basic execlist implementation we'll only need our PPGTT PDs,
> > > > > and ringbuffer addresses in order to set up the context. With previous
> > > > > patches, we have both, so start prepping the context to be load.
> > > > >
> > > > > Before running a context for the first time you must populate some
> > > > > fields in the context object. These fields begin 1 PAGE + LRCA, ie. the
> > > > > first page (in 0 based counting) of the context image. These same
> > > > > fields will be read and written to as contexts are saved and restored
> > > > > once the system is up and running.
> > > > >
> > > > > Many of these fields are completely reused from previous global
> > > > > registers: ringbuffer head/tail/control, context control matches some
> > > > > previous MI_SET_CONTEXT flags, and page directories. There are other
> > > > > fields which we don't touch which we may want in the future.
> > > > >
> > > > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > > > >
> > > > > v2: CTX_LRI_HEADER_0 is MI_LOAD_REGISTER_IMM(14) for render and (11)
> > > > > for other engines.
> > > > >
> > > > > Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> > > > >
> > > > > v3: Several rebases and general changes to the code.
> > > > >
> > > > > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_lrc.c | 145 ++++++++++++++++++++++++++++++++++++++--
> > > > > 1 file changed, 138 insertions(+), 7 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_lrc.c b/drivers/gpu/drm/i915/i915_lrc.c
> > > > > index 40dfa95..f0176ff 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_lrc.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_lrc.c
> > > > > @@ -43,6 +43,38 @@
> > > > >
> > > > > #define GEN8_LR_CONTEXT_SIZE (21 * PAGE_SIZE)
> > > > >
> > > > > +#define RING_ELSP(ring) ((ring)->mmio_base+0x230)
> > > > > +#define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
> > > > > +
> > > > > +#define CTX_LRI_HEADER_0 0x01
> > > > > +#define CTX_CONTEXT_CONTROL 0x02
> > > > > +#define CTX_RING_HEAD 0x04
> > > > > +#define CTX_RING_TAIL 0x06
> > > > > +#define CTX_RING_BUFFER_START 0x08
> > > > > +#define CTX_RING_BUFFER_CONTROL 0x0a
> > > > > +#define CTX_BB_HEAD_U 0x0c
> > > > > +#define CTX_BB_HEAD_L 0x0e
> > > > > +#define CTX_BB_STATE 0x10
> > > > > +#define CTX_SECOND_BB_HEAD_U 0x12
> > > > > +#define CTX_SECOND_BB_HEAD_L 0x14
> > > > > +#define CTX_SECOND_BB_STATE 0x16
> > > > > +#define CTX_BB_PER_CTX_PTR 0x18
> > > > > +#define CTX_RCS_INDIRECT_CTX 0x1a
> > > > > +#define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
> > > > > +#define CTX_LRI_HEADER_1 0x21
> > > > > +#define CTX_CTX_TIMESTAMP 0x22
> > > > > +#define CTX_PDP3_UDW 0x24
> > > > > +#define CTX_PDP3_LDW 0x26
> > > > > +#define CTX_PDP2_UDW 0x28
> > > > > +#define CTX_PDP2_LDW 0x2a
> > > > > +#define CTX_PDP1_UDW 0x2c
> > > > > +#define CTX_PDP1_LDW 0x2e
> > > > > +#define CTX_PDP0_UDW 0x30
> > > > > +#define CTX_PDP0_LDW 0x32
> > > > > +#define CTX_LRI_HEADER_2 0x41
> > > > > +#define CTX_R_PWR_CLK_STATE 0x42
> > > > > +#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
> > > > > +
> > > > > struct i915_hw_context *
> > > > > gen8_gem_create_context(struct drm_device *dev,
> > > > > struct intel_engine *ring,
> > > > > @@ -51,6 +83,9 @@ gen8_gem_create_context(struct drm_device *dev,
> > > > > {
> > > > > struct i915_hw_context *ctx = NULL;
> > > > > struct drm_i915_gem_object *ring_obj = NULL;
> > > > > + struct i915_hw_ppgtt *ppgtt = NULL;
> > > > > + struct page *page;
> > > > > + uint32_t *reg_state;
> > > > > int ret;
> > > > >
> > > > > ctx = i915_gem_create_context(dev, file_priv, create_vm);
> > > > > @@ -79,18 +114,114 @@ gen8_gem_create_context(struct drm_device *dev,
> > > > >
> > > > > /* Failure at this point is almost impossible */
> > > > > ret = i915_gem_object_set_to_gtt_domain(ring_obj, true);
> > > > > - if (ret) {
> > > > > - i915_gem_object_ggtt_unpin(ring_obj);
> > > > > - drm_gem_object_unreference(&ring_obj->base);
> > > > > - i915_gem_object_ggtt_unpin(ctx->obj);
> > > > > - i915_gem_context_unreference(ctx);
> > > > > - return ERR_PTR(ret);
> > > > > - }
> > > > > + if (ret)
> > > > > + goto destroy_ring_obj;
> > > > >
> > > > > ctx->ringbuf = &ring->default_ringbuf;
> > > > > ctx->ringbuf->obj = ring_obj;
> > > > >
> > > > > + ppgtt = ctx_to_ppgtt(ctx);
> > > > > +
> > > > > + ret = i915_gem_object_set_to_cpu_domain(ctx->obj, true);
> > > > > + if (ret)
> > > > > + goto destroy_ring_obj;
> > > > > +
> > > > > + ret = i915_gem_object_get_pages(ctx->obj);
> > > > > + if (ret)
> > > > > + goto destroy_ring_obj;
> > > > > +
> > > > > + i915_gem_object_pin_pages(ctx->obj);
> > > > > +
> > > > > + /* The second page of the context object contains some fields which must
> > > > > + * be set up prior to the first execution.
> > > > > + */
> > > > > + page = i915_gem_object_get_page(ctx->obj, 1);
> > > > > + reg_state = kmap_atomic(page);
> > > > > +
> > > > > + if (ring->id == RCS)
> > > > > + reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
> > > > > + else
> > > > > + reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
> > > > > + reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
> > > > > + reg_state[CTX_CONTEXT_CONTROL+1] = (1<<3) | MI_RESTORE_INHIBIT;
> > > > > + reg_state[CTX_CONTEXT_CONTROL+1] |= reg_state[CTX_CONTEXT_CONTROL+1] << 16;
> > > > > + reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
> > > > > + reg_state[CTX_RING_HEAD+1] = 0;
> > > > > + reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
> > > > > + reg_state[CTX_RING_TAIL+1] = 0;
> > > > > + reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
> > > > > + reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
> > > > > + reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
> > > > > + reg_state[CTX_RING_BUFFER_CONTROL+1] = (31 * PAGE_SIZE) | RING_VALID;
> > > > > + reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
> > > > > + reg_state[CTX_BB_HEAD_U+1] = 0;
> > > > > + reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
> > > > > + reg_state[CTX_BB_HEAD_L+1] = 0;
> > > > > + reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
> > > > > + reg_state[CTX_BB_STATE+1] = (1<<5);
> > > > > + reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
> > > > > + reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
> > > > > + reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
> > > > > + reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
> > > > > + reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
> > > > > + reg_state[CTX_SECOND_BB_STATE+1] = 0;
> > > > > + if (ring->id == RCS) {
> > > > > + reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
> > > > > + reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
> > > > > + reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
> > > > > + reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
> > > > > + reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
> > > > > + reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
> > > > > + }
> > > > > +
> > > > > + reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
> > > > > + reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
> > > > > + reg_state[CTX_CTX_TIMESTAMP+1] = 0;
> > > > > + reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
> > > > > + reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
> > > > > + reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
> > > > > + reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
> > > > > + reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
> > > > > + reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
> > > > > + reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
> > > > > + reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
> > > > > + reg_state[CTX_PDP3_UDW+1] = ppgtt->pd_dma_addr[3] >> 32;
> > > > > + reg_state[CTX_PDP3_LDW+1] = ppgtt->pd_dma_addr[3];
> > > > > + reg_state[CTX_PDP2_UDW+1] = ppgtt->pd_dma_addr[2] >> 32;
> > > > > + reg_state[CTX_PDP2_LDW+1] = ppgtt->pd_dma_addr[2];
> > > > > + reg_state[CTX_PDP1_UDW+1] = ppgtt->pd_dma_addr[1] >> 32;
> > > > > + reg_state[CTX_PDP1_LDW+1] = ppgtt->pd_dma_addr[1];
> > > > > + reg_state[CTX_PDP0_UDW+1] = ppgtt->pd_dma_addr[0] >> 32;
> > > > > + reg_state[CTX_PDP0_LDW+1] = ppgtt->pd_dma_addr[0];
> > > > > + if (ring->id == RCS) {
> > > > > + reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
> > > > > + reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
> > > >
> > > > You're writing the MMIO address for the R_PWR_CLK_STATE register to this
> > > > field. Shouldn't this receive the value we want programmed to the register?
> > > >
> > >
> > > Oh, nevermind. I understand now.
> > > -Jeff
> > >
> > To clarify my comments...I was at first confused by the need to specify the
> > R_PWR_CLK_STATE register address in the logical context, thinking that only
> > the desired value needed to be specified. But I see now that the programming
> > model is to specify the MI_LOAD_REGISTER_IMM command, followed by the address
> > at which to load, followed by the value to load.
> >
> > Reflecting on my initial confusion, would it be clearer to provide names for
> > each dword position in the context image, rather than using an unnamed offset
> > like CTX_R_PWR_CLK_STATE+1? Example:
> >
> > reg_state[CTX_R_PWR_CLK_STATE_ADDR] = 0x20c8
> > reg_state[CTX_R_PWR_CLK_STATE_DATA] = 0;
>
> Usually when we emit batches in userspace (and the context is nothing else
> really) we have some OUT_BATCH macro which writes the dword and increments
> the pointer. Since MI_LOAD_REGISTER_IMM is multi-length we could add a
> OUT_BATCH_REG_WRITE(reg, value) which does both dword emissions.
>
> That should clarify a lot what's going on here. We might even completely
> drop all the offset #defines and replace them with a few comments or so.
> -Daniel
>
OK, now I get it. My mistake was in thinking the context image is just pure
state that hardware already knows how to restore. But as you say it is more
like a batch which includes the state *and* the MI_LOAD_REGISTER_IMM commands
required to restore. So in that sense I understand that the approach here to
initilize the context is much like constructing a batch. But later when we
want to update the value of a context field we have (in a later patch of this
series):
reg_state[CTX_RING_TAIL+1] = value;
This is a bit obscure when occurring by itself and not in the flow of
initializing the context (batch). The same will be true when we add management
of the CTX_R_PWR_CLK_STATE value dword.
-Jeff
> >
> > Jeff
> > > > > + reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
> > > > > + }
> > > > > +
> > > > > +#if 0
> > > > > + /* Offsets not yet defined for these */
> > > > > + reg_state[CTX_GPGPU_CSR_BASE_ADDRESS[] = ;
> > > > > + reg_state[CTX_GPGPU_CSR_BASE_ADDRESS+1] = 0;
> > > > > +#endif
> > > > > +
> > > > > + kunmap_atomic(reg_state);
> > > > > +
> > > > > + ctx->obj->dirty = 1;
> > > > > + set_page_dirty(page);
> > > > > + i915_gem_object_unpin_pages(ctx->obj);
> > > > > +
> > > > > return ctx;
> > > > > +
> > > > > +destroy_ring_obj:
> > > > > + i915_gem_object_ggtt_unpin(ring_obj);
> > > > > + drm_gem_object_unreference(&ring_obj->base);
> > > > > + ctx->ringbuf->obj = NULL;
> > > > > + ctx->ringbuf = NULL;
> > > > > + i915_gem_object_ggtt_unpin(ctx->obj);
> > > > > + i915_gem_context_unreference(ctx);
> > > > > +
> > > > > + return ERR_PTR(ret);
> > > > > }
> > > > >
> > > > > void gen8_gem_context_fini(struct drm_device *dev)
> > > > > --
> > > > > 1.9.0
> > > > >
> > > > > _______________________________________________
> > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2014-04-15 22:24 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-27 17:59 [PATCH 00/49] Execlists oscar.mateo
2014-03-27 17:59 ` [PATCH 01/49] drm/i915/bdw: Macro to distinguish LRCs (Logical Ring Contexts) oscar.mateo
2014-03-27 17:59 ` [PATCH 02/49] drm/i915: s/for_each_ring/for_each_active_ring oscar.mateo
2014-03-27 17:59 ` [PATCH 03/49] drm/i915: for_each_ring oscar.mateo
2014-03-27 17:59 ` [PATCH 04/49] drm/i915: Simplify a couple of functions thanks to for_each_ring oscar.mateo
2014-03-27 17:59 ` [PATCH 05/49] drm/i915: Extract trivial parts of ring init (early init) oscar.mateo
2014-03-27 17:59 ` [PATCH 06/49] drm/i915/bdw: New file for logical ring contexts and execlists oscar.mateo
2014-03-27 17:59 ` [PATCH 07/49] drm/i915/bdw: Rework init code for gen8 contexts oscar.mateo
2014-03-27 17:59 ` [PATCH 08/49] drm/i915: Make i915_gem_create_context outside accessible oscar.mateo
2014-03-27 17:59 ` [PATCH 09/49] drm/i915: Extract ringbuffer obj alloc & destroy oscar.mateo
2014-03-27 17:59 ` [PATCH 10/49] drm/i915: s/intel_ring_buffer/intel_engine oscar.mateo
2014-03-27 17:59 ` [PATCH 11/49] drm/i915: Split the ringbuffers and the rings oscar.mateo
2014-03-27 17:59 ` [PATCH 12/49] drm/i915: Rename functions that mention ringbuffers (meaning rings) oscar.mateo
2014-03-27 17:59 ` [PATCH 13/49] drm/i915/bdw: Execlists ring tail writing oscar.mateo
2014-03-27 17:13 ` Mateo Lozano, Oscar
2014-03-27 17:59 ` [PATCH 14/49] drm/i915/bdw: LR context ring init oscar.mateo
2014-03-27 17:59 ` [PATCH 15/49] drm/i915/bdw: GEN8 semaphoreless ring add request oscar.mateo
2014-03-27 17:59 ` [PATCH 16/49] drm/i915/bdw: GEN8 new ring flush oscar.mateo
2014-03-27 17:59 ` [PATCH 17/49] drm/i915/bdw: A bit more advanced context init/fini oscar.mateo
2014-04-01 0:38 ` Damien Lespiau
2014-04-01 13:47 ` Mateo Lozano, Oscar
2014-04-01 13:51 ` Damien Lespiau
2014-04-01 19:18 ` Ben Widawsky
2014-04-01 21:05 ` Damien Lespiau
2014-04-02 4:07 ` Ben Widawsky
2014-03-27 17:59 ` [PATCH 18/49] drm/i915/bdw: Allocate ringbuffer for LR contexts oscar.mateo
2014-03-27 17:59 ` [PATCH 19/49] drm/i915/bdw: Populate LR contexts (somewhat) oscar.mateo
2014-04-01 0:00 ` Damien Lespiau
2014-04-01 13:33 ` Mateo Lozano, Oscar
2014-04-15 16:00 ` Jeff McGee
2014-04-15 16:10 ` Jeff McGee
2014-04-15 19:51 ` Daniel Vetter
2014-04-15 20:43 ` Jeff McGee
2014-04-15 21:08 ` Daniel Vetter
2014-04-15 22:32 ` Jeff McGee [this message]
2014-04-16 6:04 ` Daniel Vetter
2014-03-27 17:59 ` [PATCH 20/49] drm/i915/bdw: Status page for LR contexts oscar.mateo
2014-03-27 17:59 ` [PATCH 21/49] drm/i915/bdw: Enable execlists in the hardware oscar.mateo
2014-03-27 17:59 ` [PATCH 22/49] drm/i915/bdw: Plumbing for user LR context switching oscar.mateo
2014-03-27 17:59 ` [PATCH 23/49] drm/i915: s/__intel_ring_advance/intel_ringbuffer_advance_and_submit oscar.mateo
2014-03-27 17:59 ` [PATCH 24/49] drm/i915/bdw: Write a new set of context-aware ringbuffer management functions oscar.mateo
2014-03-27 17:59 ` [PATCH 25/49] drm/i915: Final touches to LR contexts plumbing and refactoring oscar.mateo
2014-03-27 17:59 ` [PATCH 26/49] drm/i915/bdw: Set the request context information correctly in the LRC case oscar.mateo
2014-03-27 17:59 ` [PATCH 27/49] drm/i915/bdw: Prepare for user-created LR contexts oscar.mateo
2014-03-27 17:59 ` [PATCH 28/49] drm/i915/bdw: Start creating & destroying user " oscar.mateo
2014-03-27 17:59 ` [PATCH 29/49] drm/i915/bdw: Pin context pages at context create time oscar.mateo
2014-03-27 17:59 ` [PATCH 30/49] drm/i915/bdw: Extract LR context object populating oscar.mateo
2014-03-27 18:00 ` [PATCH 31/49] drm/i915/bdw: Introduce dependent contexts oscar.mateo
2014-03-27 17:21 ` Mateo Lozano, Oscar
2014-04-09 16:54 ` Mateo Lozano, Oscar
2014-03-27 18:00 ` [PATCH 32/49] drm/i915/bdw: Create stand-alone and " oscar.mateo
2014-03-27 18:00 ` [PATCH 33/49] drm/i915/bdw: Allow non-default, non-render user LR contexts oscar.mateo
2014-03-27 18:00 ` [PATCH 34/49] drm/i915/bdw: Fix reset stats ioctl with " oscar.mateo
2014-03-27 18:00 ` [PATCH 35/49] drm/i915: Allocate an integer ID for each new file descriptor oscar.mateo
2014-03-27 18:00 ` [PATCH 36/49] drm/i915/bdw: Prepare for a 20-bits globally unique submission ID oscar.mateo
2014-03-27 18:00 ` [PATCH 37/49] drm/i915/bdw: Implement context switching (somewhat) oscar.mateo
2014-03-27 18:00 ` [PATCH 38/49] drm/i915/bdw: Add forcewake lock around ELSP writes oscar.mateo
2014-03-27 18:00 ` [PATCH 39/49] drm/i915/bdw: Swap the PPGTT PDPs, LRC style oscar.mateo
2014-03-31 16:42 ` Damien Lespiau
2014-04-01 13:42 ` Mateo Lozano, Oscar
2014-04-02 13:47 ` Damien Lespiau
2014-04-09 7:56 ` Mateo Lozano, Oscar
2014-03-27 18:00 ` [PATCH 40/49] drm/i915/bdw: Write the tail pointer, " oscar.mateo
2014-03-27 18:00 ` [PATCH 41/49] drm/i915/bdw: LR context switch interrupts oscar.mateo
2014-04-02 11:42 ` Damien Lespiau
2014-04-02 11:49 ` Daniel Vetter
2014-04-02 12:56 ` Damien Lespiau
2014-03-27 18:00 ` [PATCH 42/49] drm/i915/bdw: Get prepared for a two-stage execlist submit process oscar.mateo
2014-04-04 11:12 ` Damien Lespiau
2014-04-04 13:24 ` Damien Lespiau
2014-04-09 7:57 ` Mateo Lozano, Oscar
2014-03-27 18:00 ` [PATCH 43/49] drm/i915/bdw: Handle context switch events oscar.mateo
2014-04-03 14:24 ` Damien Lespiau
2014-04-09 8:15 ` Mateo Lozano, Oscar
2014-04-26 0:53 ` Robert Beckett
2014-04-28 14:43 ` Mateo Lozano, Oscar
2014-03-27 18:00 ` [PATCH 44/49] drm/i915/bdw: Display execlists info in debugfs oscar.mateo
2014-04-07 19:19 ` Damien Lespiau
2014-03-27 18:00 ` [PATCH 45/49] drm/i915/bdw: Display context ringbuffer " oscar.mateo
2014-03-27 18:00 ` [PATCH 46/49] drm/i915/bdw: Start queueing contexts to be submitted oscar.mateo
2014-03-27 18:00 ` [PATCH 47/49] drm/i915/bdw: Always write seqno to default context oscar.mateo
2014-03-27 18:00 ` [PATCH 48/49] drm/i915/bdw: Enable logical ring contexts oscar.mateo
2014-03-27 18:00 ` [PATCH 49/49] drm/i915/bdw: Document execlists and " oscar.mateo
2014-04-07 18:12 ` [PATCH 00/49] Execlists Damien Lespiau
2014-04-07 21:32 ` Daniel Vetter
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