From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 2/2] drm/i915: Enable PM Interrupts target via Display Interface. Date: Wed, 16 Apr 2014 16:32:15 +0300 Message-ID: <20140416133215.GJ18465@intel.com> References: <1397495475-22667-1-git-send-email-deepak.s@intel.com> <1397495475-22667-3-git-send-email-deepak.s@intel.com> <20140414193655.GO18465@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 997F46EA02 for ; Wed, 16 Apr 2014 06:32:24 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140414193655.GO18465@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: deepak.s@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Apr 14, 2014 at 10:36:55PM +0300, Ville Syrj=E4l=E4 wrote: > On Mon, Apr 14, 2014 at 10:41:15PM +0530, deepak.s@intel.com wrote: > > From: Deepak S > > = > > In BDW, Apart from unmasking up/down threshold interrupts. we need > > to umask bit 32 of PM_INTRMASK to route interrupts to target via Display > > Interface. > > = > > Signed-off-by: Deepak S > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_pm.c | 2 ++ > > 2 files changed, 3 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index c2dd436..8c7841b 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -5105,6 +5105,7 @@ enum punit_power_well { > > #define GEN6_RC6p_THRESHOLD 0xA0BC > > #define GEN6_RC6pp_THRESHOLD 0xA0C0 > > #define GEN6_PMINTRMSK 0xA168 > > +#define GEN8_PMINTR_REDIRECT_TO_NON_DISP 0x7FFFFFFF > = > Defining is as (1<<31) would make more sense to me. > = > > = > > #define GEN6_PMISR 0x44020 > > #define GEN6_PMIMR 0x44024 /* rps_lock */ > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index 27b64ab..6b123cd 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3066,6 +3066,8 @@ static u32 gen6_rps_pm_mask(struct drm_i915_priva= te *dev_priv, u8 val) > > if (INTEL_INFO(dev_priv->dev)->gen <=3D 7 && !IS_HASWELL(dev_priv->de= v)) > > mask |=3D GEN6_PM_RP_UP_EI_EXPIRED; > > = > > + mask &=3D GEN8_PMINTR_REDIRECT_TO_NON_DISP; > > + > > return ~mask; Oh and just noticed this doesn't actually do anything. & must come after ~ to get the expected result. > > } > > = > > -- = > > 1.8.5.2 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Ville Syrj=E4l=E4 > Intel OTC -- = Ville Syrj=E4l=E4 Intel OTC