Re: [PATCH 06/24] drm/i915: Disable/enable planes as the first/last thing during modeset on ILK+

Paulo Zanoni
2014-04-07T19:51:22Z

2014-03-07 13:32 GMT-03:00 <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We already do this for HSW, but doing it makes sense for everything else
> as well. Extend it for ILK/SNB/IVB since that's where the new watermark
> code is used.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> ---
> drivers/gpu/drm/i915/intel_display.c | 115 +++++++++++++++--------------------
> 1 file changed, 48 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c309dd1..7938556 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3543,6 +3543,48 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
> hsw_enable_ips(intel_crtc);
> }
>
> +static void ilk_crtc_enable_planes(struct drm_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + int pipe = intel_crtc->pipe;
> + int plane = intel_crtc->plane;
> +
> + intel_enable_primary_plane(dev_priv, plane, pipe);
> + intel_enable_planes(crtc);
> + intel_crtc_update_cursor(crtc, true);
> +
> + hsw_enable_ips(intel_crtc);
> +
> + mutex_lock(&dev->struct_mutex);
> + intel_update_fbc(dev);
> + mutex_unlock(&dev->struct_mutex);
> +
> + drm_vblank_on(dev, pipe);
> +}
> +
> +static void ilk_crtc_disable_planes(struct drm_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + int pipe = intel_crtc->pipe;
> + int plane = intel_crtc->plane;
> +
> + intel_crtc_wait_for_pending_flips(crtc);
> + drm_vblank_off(dev, pipe);
> +
> + if (dev_priv->fbc.plane == plane)
> + intel_disable_fbc(dev);
> +
> + hsw_disable_ips(intel_crtc);
> +
> + intel_crtc_update_cursor(crtc, false);
> + intel_disable_planes(crtc);
> + intel_disable_primary_plane(dev_priv, plane, pipe);
> +}
> +
> static void ironlake_crtc_enable(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> @@ -3550,7 +3592,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> int pipe = intel_crtc->pipe;
> - int plane = intel_crtc->plane;
>
> WARN_ON(!crtc->enabled);
>
> @@ -3586,23 +3627,18 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>
> intel_update_watermarks(crtc);
> intel_enable_pipe(intel_crtc);
> - intel_enable_primary_plane(dev_priv, plane, pipe);
> - intel_enable_planes(crtc);
> - intel_crtc_update_cursor(crtc, true);
>
> if (intel_crtc->config.has_pch_encoder)
> ironlake_pch_enable(crtc);
>
> - mutex_lock(&dev->struct_mutex);
> - intel_update_fbc(dev);
> - mutex_unlock(&dev->struct_mutex);
> -
> for_each_encoder_on_crtc(dev, crtc, encoder)
> encoder->enable(encoder);
>
> if (HAS_PCH_CPT(dev))
> cpt_verify_modeset(dev, intel_crtc->pipe);
>
> + ilk_crtc_enable_planes(crtc);
> +
> /*
> * There seems to be a race in PCH platform hw (at least on some
> * outputs) where an enabled pipe still completes any pageflip right
> @@ -3612,8 +3648,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> * happening.
> */
> intel_wait_for_vblank(dev, intel_crtc->pipe);
> -
> - drm_vblank_on(dev, pipe);
> }
>
> /* IPS only exists on ULT machines and is tied to pipe A. */
> @@ -3622,49 +3656,6 @@ static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
> return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
> }
>
> -static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
> -{
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - int pipe = intel_crtc->pipe;
> - int plane = intel_crtc->plane;
> -
> - intel_enable_primary_plane(dev_priv, plane, pipe);
> - intel_enable_planes(crtc);
> - intel_crtc_update_cursor(crtc, true);
> -
> - hsw_enable_ips(intel_crtc);
> -
> - mutex_lock(&dev->struct_mutex);
> - intel_update_fbc(dev);
> - mutex_unlock(&dev->struct_mutex);
> -
> - drm_vblank_on(dev, pipe);
> -}
> -
> -static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
> -{
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - int pipe = intel_crtc->pipe;
> - int plane = intel_crtc->plane;
> -
> - intel_crtc_wait_for_pending_flips(crtc);
> - drm_vblank_off(dev, pipe);
> -
> - /* FBC must be disabled before disabling the plane on HSW. */
> - if (dev_priv->fbc.plane == plane)
> - intel_disable_fbc(dev);
> -
> - hsw_disable_ips(intel_crtc);
> -
> - intel_crtc_update_cursor(crtc, false);
> - intel_disable_planes(crtc);
> - intel_disable_primary_plane(dev_priv, plane, pipe);
> -}
> -
> /*
> * This implements the workaround described in the "notes" section of the mode
> * set sequence documentation. When going from no pipes or single pipe to
> @@ -3747,7 +3738,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> /* If we change the relative order between pipe/planes enabling, we need
> * to change the workaround. */
> haswell_mode_set_planes_workaround(intel_crtc);
> - haswell_crtc_enable_planes(crtc);
> + ilk_crtc_enable_planes(crtc);
> }
>
> static void ironlake_pfit_disable(struct intel_crtc *crtc)
> @@ -3772,26 +3763,16 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> int pipe = intel_crtc->pipe;
> - int plane = intel_crtc->plane;
> u32 reg, temp;
>
> -
> if (!intel_crtc->active)
> return;
>
> + ilk_crtc_disable_planes(crtc);
> +
> for_each_encoder_on_crtc(dev, crtc, encoder)
> encoder->disable(encoder);
>
> - intel_crtc_wait_for_pending_flips(crtc);
> - drm_vblank_off(dev, pipe);
> -
> - if (dev_priv->fbc.plane == plane)
> - intel_disable_fbc(dev);
> -
> - intel_crtc_update_cursor(crtc, false);
> - intel_disable_planes(crtc);
> - intel_disable_primary_plane(dev_priv, plane, pipe);
> -
> if (intel_crtc->config.has_pch_encoder)
> intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
>
> @@ -3850,7 +3831,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
> if (!intel_crtc->active)
> return;
>
> - haswell_crtc_disable_planes(crtc);
> + ilk_crtc_disable_planes(crtc);
>
> for_each_encoder_on_crtc(dev, crtc, encoder) {
> intel_opregion_notify_encoder(encoder, false);
> --
> 1.8.3.2
>
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--
Paulo Zanoni