From: Ben Widawsky <ben@bwidawsk.net>
To: deepak.s@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 06/10] drm/i915/chv: Streamline CHV forcewake stuff
Date: Fri, 25 Apr 2014 15:24:40 -0700 [thread overview]
Message-ID: <20140425222440.GG4167@bwidawsk.net> (raw)
In-Reply-To: <1398067454-7581-7-git-send-email-deepak.s@linux.intel.com>
On Mon, Apr 21, 2014 at 01:34:10PM +0530, deepak.s@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Streamline the CHV forcewake functions just like was done for VLV.
>
> This will also fix a bug in accessing the common well registers,
> where we'd end up trying to wake up the wells too many times
> since we'd call force_wake_get/put twice per register access, with
> FORCEFAKE_ALL both times.
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Already reviewed. I guess this patch makes what I was requesting earlier
a bit harder to implement. :-(
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 88 ++++++++++++++-----------------------
> 1 file changed, 32 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 11741e4..f1264e2 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -619,35 +619,22 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> unsigned fwengine = 0; \
> REG_READ_HEADER(x); \
> if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> - fwengine = FORCEWAKE_RENDER; \
> - } \
> - else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> - fwengine = FORCEWAKE_MEDIA; \
> - } \
> - else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> - fwengine = FORCEWAKE_ALL; \
> - } \
> - if (FORCEWAKE_RENDER & fwengine) { \
> - if (dev_priv->uncore.fw_rendercount++ == 0) \
> - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> - fwengine); \
> - } \
> - if (FORCEWAKE_MEDIA & fwengine) { \
> - if (dev_priv->uncore.fw_mediacount++ == 0) \
> - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> - fwengine); \
> + if (dev_priv->uncore.fw_rendercount == 0) \
> + fwengine = FORCEWAKE_RENDER; \
> + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> + if (dev_priv->uncore.fw_mediacount == 0) \
> + fwengine = FORCEWAKE_MEDIA; \
> + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> + if (dev_priv->uncore.fw_rendercount == 0) \
> + fwengine |= FORCEWAKE_RENDER; \
> + if (dev_priv->uncore.fw_mediacount == 0) \
> + fwengine |= FORCEWAKE_MEDIA; \
> } \
> + if (fwengine) \
> + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
> val = __raw_i915_read##x(dev_priv, reg); \
> - if (FORCEWAKE_RENDER & fwengine) { \
> - if (--dev_priv->uncore.fw_rendercount == 0) \
> - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> - fwengine); \
> - } \
> - if (FORCEWAKE_MEDIA & fwengine) { \
> - if (--dev_priv->uncore.fw_mediacount == 0) \
> - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> - fwengine); \
> - } \
> + if (fwengine) \
> + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
> REG_READ_FOOTER; \
> }
>
> @@ -781,38 +768,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
> static void \
> chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> unsigned fwengine = 0; \
> - bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
> + bool shadowed = is_gen8_shadowed(dev_priv, reg); \
> REG_WRITE_HEADER; \
> - if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> - fwengine = FORCEWAKE_RENDER; \
> - } \
> - else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> - fwengine = FORCEWAKE_MEDIA; \
> - } \
> - else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> - fwengine = FORCEWAKE_ALL; \
> - } \
> - if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
> - if (dev_priv->uncore.fw_rendercount++ == 0) \
> - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> - fwengine); \
> - } \
> - if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
> - if (dev_priv->uncore.fw_mediacount++ == 0) \
> - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
> - fwengine); \
> + if (!shadowed) { \
> + if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> + if (dev_priv->uncore.fw_rendercount == 0) \
> + fwengine = FORCEWAKE_RENDER; \
> + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> + if (dev_priv->uncore.fw_mediacount == 0) \
> + fwengine = FORCEWAKE_MEDIA; \
> + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> + if (dev_priv->uncore.fw_rendercount == 0) \
> + fwengine |= FORCEWAKE_RENDER; \
> + if (dev_priv->uncore.fw_mediacount == 0) \
> + fwengine |= FORCEWAKE_MEDIA; \
> + } \
Nice target here we could extract out as common between read/write.
> } \
> + if (fwengine) \
> + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
> __raw_i915_write##x(dev_priv, reg, val); \
> - if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
> - if (--dev_priv->uncore.fw_rendercount == 0) \
> - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> - fwengine); \
> - } \
> - if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
> - if (--dev_priv->uncore.fw_mediacount == 0) \
> - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
> - fwengine); \
> - } \
> + if (fwengine) \
> + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
> REG_WRITE_FOOTER; \
> }
>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
--
Ben Widawsky, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2014-04-25 22:24 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-21 8:04 [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler deepak.s
2014-04-21 8:04 ` [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface deepak.s
2014-04-25 21:33 ` Ben Widawsky
2014-04-21 8:04 ` [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview deepak.s
2014-04-25 21:42 ` Ben Widawsky
2014-04-25 21:44 ` Ben Widawsky
2014-04-28 15:11 ` Deepak S
2014-04-28 14:29 ` Imre Deak
2014-04-28 14:45 ` Daniel Vetter
2014-04-28 15:02 ` Deepak S
2014-04-28 15:10 ` Deepak S
2014-04-21 8:04 ` [PATCH 04/10] drm/i915/chv: Added CHV specific register read and write deepak.s
2014-04-25 21:54 ` Ben Widawsky
2014-05-05 5:55 ` Deepak S
2014-04-21 8:04 ` [PATCH 05/10] drm/i915/chv: Enable RPS (Turbo) for Cheeryview deepak.s
2014-04-25 22:17 ` Ben Widawsky
2014-04-21 8:04 ` [PATCH 06/10] drm/i915/chv: Streamline CHV forcewake stuff deepak.s
2014-04-25 22:24 ` Ben Widawsky [this message]
2014-04-21 8:04 ` [PATCH 07/10] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
2014-04-21 8:04 ` [PATCH 08/10] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
2014-04-25 22:26 ` Ben Widawsky
2014-04-21 8:04 ` [PATCH 09/10] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
2014-04-25 22:28 ` Ben Widawsky
2014-04-21 8:04 ` [PATCH 10/10] drm/i915/chv: Freq(opcode) request value for CHV deepak.s
2014-04-25 22:32 ` Ben Widawsky
2014-04-25 21:08 ` [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler Ben Widawsky
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20140425222440.GG4167@bwidawsk.net \
--to=ben@bwidawsk.net \
--cc=deepak.s@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox