Re: [PATCH 08/10] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV

[Ben Widawsky <ben@bwidawsk.net>]

On Mon, Apr 21, 2014 at 01:34:12PM +0530, deepak.s@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> CHV uses the gen8 shadow register mechanism so we shouldn't be
> checking the GT FIFO status.
> 
> This effectively removes the posting read, so add an explicit
> posting read using FORCEWAKE_ACK_VLV (which is what use in
> vlv_forcewake_reset()).
> 
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index b0f0651..7170506 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -248,9 +248,10 @@ static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
>  		__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
>  				_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
>  
> -	/* The below doubles as a POSTING_READ */
> -	gen6_gt_check_fifodbg(dev_priv);
> -
> +	/* something from same cacheline, but !FORCEWAKE_VLV */
> +	__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
> +	if (!IS_CHERRYVIEW(dev_priv->dev))
> +		gen6_gt_check_fifodbg(dev_priv);

You could save a read for the VLV case, but no big deal.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

>  }
>  
>  static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
> -- 
> 1.9.1
> 
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-- 
Ben Widawsky, Intel Open Source Technology Center
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