From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 03/10] drm/i915/chv: Enable Render Standby
 (RC6) for Cheeryview
Date: Mon, 28 Apr 2014 16:45:32 +0200
Message-ID: <20140428144532.GF32404@phenom.ffwll.local>
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To: Imre Deak <imre.deak@intel.com>
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On Mon, Apr 28, 2014 at 05:29:46PM +0300, Imre Deak wrote:
> > +static void cherryview_setup_pctx(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	unsigned long pctx_paddr;
> > +	struct i915_gtt *gtt = &dev_priv->gtt;
> > +	u32 pcbr;
> > +	int pctx_size = 32*1024;
> > +
> > +	pcbr = I915_READ(VLV_PCBR);
> > +	if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
> > +		/*
> > +		 * From the Gunit register HAS:
> > +		 * The Gfx driver is expected to program this register and ensure
> > +		 * proper allocation within Gfx stolen memory.  For example, this
> > +		 * register should be programmed such than the PCBR range does not
> > +		 * overlap with other relevant ranges.
> > +		 */
> > +		pctx_paddr = (dev_priv->mm.stolen_base + gtt->stolen_size - pctx_size);
> 
> This area should be reserved.

We've had a really lengthy discussion internally about the bios-reserved
chunk in stolen. It was stalled due to (imo unjustified) fear to leak
information what the bios actually uses this for.

If we need to reserve more of stolen than we currently do we need to pick
up that approach again instead of adding more bandaids.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch