Re: [PATCH 13/14] drm/i915/bdw: Disable idle DOP clock gating

[Daniel Vetter <daniel@ffwll.ch>]

On Mon, Apr 28, 2014 at 09:37:36AM -0700, Volkin, Bradley D wrote:
> Reviewed-by: Brad Volkin <bradley.d.volkin@intel.com>
> 
> On Fri, Apr 18, 2014 at 02:04:29PM -0700, Rodrigo Vivi wrote:
> > From: Ben Widawsky <benjamin.widawsky@intel.com>
> > 
> > It seems we need this at least for the current platforms we have, but
> > probably not later. In any event, it should cause too much harm as we do
> > the same thing on several other platforms.
> > 
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

All three patches from Ben merged, thanks.
-Daniel

> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index a66000c..8d40786 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4924,6 +4924,10 @@ static void gen8_init_clock_gating(struct drm_device *dev)
> >  	I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> >  		   _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
> >  
> > +	/* WaDisableDopClockGating:bdw May not be needed for production */
> > +	I915_WRITE(GEN7_ROW_CHICKEN2,
> > +		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> > +
> >  	/* WaSwitchSolVfFArbitrationPriority:bdw */
> >  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> >  
> > -- 
> > 1.8.3.1
> > 
> > _______________________________________________
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> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch