From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 13/14] drm/i915/bdw: Disable idle DOP clock gating Date: Tue, 29 Apr 2014 10:50:56 +0200 Message-ID: <20140429085056.GJ32404@phenom.ffwll.local> References: <1397855070-4480-1-git-send-email-rodrigo.vivi@gmail.com> <1397855070-4480-14-git-send-email-rodrigo.vivi@gmail.com> <20140428163736.GE25551@bdvolkin-ubuntu-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f51.google.com (mail-ee0-f51.google.com [74.125.83.51]) by gabe.freedesktop.org (Postfix) with ESMTP id A6CA06E934 for ; Tue, 29 Apr 2014 01:51:01 -0700 (PDT) Received: by mail-ee0-f51.google.com with SMTP id c13so35665eek.38 for ; Tue, 29 Apr 2014 01:51:00 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140428163736.GE25551@bdvolkin-ubuntu-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Volkin, Bradley D" Cc: "intel-gfx@lists.freedesktop.org" , Ben Widawsky , "Widawsky, Benjamin" List-Id: intel-gfx@lists.freedesktop.org On Mon, Apr 28, 2014 at 09:37:36AM -0700, Volkin, Bradley D wrote: > Reviewed-by: Brad Volkin > > On Fri, Apr 18, 2014 at 02:04:29PM -0700, Rodrigo Vivi wrote: > > From: Ben Widawsky > > > > It seems we need this at least for the current platforms we have, but > > probably not later. In any event, it should cause too much harm as we do > > the same thing on several other platforms. > > > > Signed-off-by: Ben Widawsky > > Signed-off-by: Rodrigo Vivi All three patches from Ben merged, thanks. -Daniel > > --- > > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index a66000c..8d40786 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -4924,6 +4924,10 @@ static void gen8_init_clock_gating(struct drm_device *dev) > > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > > _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); > > > > + /* WaDisableDopClockGating:bdw May not be needed for production */ > > + I915_WRITE(GEN7_ROW_CHICKEN2, > > + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); > > + > > /* WaSwitchSolVfFArbitrationPriority:bdw */ > > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); > > > > -- > > 1.8.3.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch