From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v4 0/9] drm/i915: Atomic sprites v4 Date: Tue, 29 Apr 2014 13:44:51 +0300 Message-ID: <20140429104451.GB18465@intel.com> References: <1398767752-619-1-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id DF7446E03B for ; Tue, 29 Apr 2014 03:45:04 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1398767752-619-1-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Apr 29, 2014 at 01:35:43PM +0300, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > Another posting of the atomic sprite series. Most things are reviewed, bu= t there > are a few patches in there for the scanline fixup that don't have r-bs. > = > The HSW+ situation is also still unclear. The scanline counter behaviour = depends > on either the actual DDI port used (A vs. rest) or the encoder type (HDMI= vs. DP). > If someone wants to help me find out which, grab [1] and run the resulting > intel_poller tool to figure out at which scanline the vblank irq triggers= and/or > live surface address gets updated. And naturally I forgot to specify [1]: git://gitorious.org/vsyrjala/intel-gpu-tools.git intel_poller > = > Examples from running the tool on my IVB: > = > # intel_poller -t iir -p 0 -b 0 > ... > dsl / pipe A / DEIIR[0] (pch): 1078 - 1079 > = > This tells me that the pipe A vblank bit in DEIIR is set when the scanline > counter increments from 1078 to 1079. The display mode was 1920x1080, so = this > tells us we need a +1 adjustment for the scaline counter. > = > # intel_poller -t surflive -p 0 > ... > dsl / pipe A / Surflive: 1078 - 1079 > = > which tells me that SURFLIVE updates at the same time, as was expected. > = > You can also run these tests: > # ./intel_poller -t flip -p 0 -l 1078 > # ./intel_poller -t pan -p 0 -l 1078 > = > These write the DSPSURF/OFFSET register when the scanline counter reaches= the target > value, and overwrite it again with the original value on the next scanlin= e. If the > target scanline is correctly set the picture remains shifted for the dura= tion > of the test, and if you specify any another scanline the picture should r= emain in > its original position the whole time. > = > So if someone can run these on HSW and BDW systems with both DP and HDMI = outputs > on various ports we can try to figure out what the actual rule is. > = > Ville Syrj=E4l=E4 (9): > drm/i915: Fix scanout position for real > drm/i915: Add intel_get_crtc_scanline() > drm/i915: Make sprite updates atomic > drm/i915: Perform primary enable/disable atomically with sprite > updates > drm/i915: Add pipe update trace points > drm/i915: Add a small adjustment to the pixel counter on interlaced > modes > drm/i915: Improve gen3/4 frame counter > drm/i915: Draw a picture about video timings > drm/i915: Fix gen2 and hsw scanline counter > = > drivers/gpu/drm/i915/i915_irq.c | 231 +++++++++++++++++++++--------= ------ > drivers/gpu/drm/i915/i915_trace.h | 75 ++++++++++++ > drivers/gpu/drm/i915/intel_display.c | 50 +++++++- > drivers/gpu/drm/i915/intel_drv.h | 5 + > drivers/gpu/drm/i915/intel_sprite.c | 231 +++++++++++++++++++++++++++++= ------ > 5 files changed, 463 insertions(+), 129 deletions(-) > = > -- = > 1.8.3.2 -- = Ville Syrj=E4l=E4 Intel OTC