From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 08/13] drm/i915: Implement MI decode for gen8 Date: Wed, 30 Apr 2014 14:21:15 +0300 Message-ID: <20140430112114.GI18465@intel.com> References: <1398808360-3674-1-git-send-email-benjamin.widawsky@intel.com> <1398808360-3674-9-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id E20626E077 for ; Wed, 30 Apr 2014 04:21:24 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1398808360-3674-9-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ben Widawsky Cc: Ben Widawsky , Intel GFX List-Id: intel-gfx@lists.freedesktop.org On Tue, Apr 29, 2014 at 02:52:35PM -0700, Ben Widawsky wrote: > From: Ben Widawsky > = > This is needed to implement ipehr_is_semaphore_wait > = > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_irq.c | 11 +++++------ > 1 file changed, 5 insertions(+), 6 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_= irq.c > index 2d76183..bfd21c7 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2561,12 +2561,9 @@ static bool > ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) > { > if (INTEL_INFO(dev)->gen >=3D 8) { > - /* > - * FIXME: gen8 semaphore support - currently we don't emit > - * semaphores on bdw anyway, but this needs to be addressed when > - * we merge that code. > - */ > - return false; > + /* Broadwell's semaphore wait is 3 dwords. We hope IPEHR is the > + * first dword. */ > + return (ipehr >> 23) =3D=3D 0x1c; > } else { > ipehr &=3D ~MI_SEMAPHORE_SYNC_MASK; > return ipehr =3D=3D (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | > @@ -2586,6 +2583,8 @@ semaphore_wait_to_signaller_ring(struct intel_ring_= buffer *ring, u32 ipehr) > * FIXME: gen8 semaphore support - currently we don't emit > * semaphores on bdw anyway, but this needs to be addressed when > * we merge that code. > + * > + * XXX: Gen8 needs more than just IPEHR. > */ I believe something like this should take care of the remaining gap. diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_ir= q.c index 2446e61..cd1069e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2590,19 +2590,21 @@ ipehr_is_semaphore_wait(struct drm_device *dev, u32= ipehr) } = static struct intel_ring_buffer * -semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr) +semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, + u32 ipehr, u64 offset) { struct drm_i915_private *dev_priv =3D ring->dev->dev_private; struct intel_ring_buffer *signaller; int i; = if (INTEL_INFO(dev_priv->dev)->gen >=3D 8) { - /* - * FIXME: gen8 semaphore support - currently we don't emit - * semaphores on bdw anyway, but this needs to be addressed when - * we merge that code. - */ - return NULL; + for_each_ring(signaller, dev_priv, i) { + if (ring =3D=3D signaller) + continue; + + if (offset =3D=3D signaller->semaphore.signal_gtt[ring->id]) + return signaller; + } } else { u32 sync_bits =3D ipehr & MI_SEMAPHORE_SYNC_MASK; = @@ -2627,6 +2629,7 @@ semaphore_waits_for(struct intel_ring_buffer *ring, u= 32 *seqno) { struct drm_i915_private *dev_priv =3D ring->dev->dev_private; u32 cmd, ipehr, head; + u64 offset =3D 0; int i; = ipehr =3D I915_READ(RING_IPEHR(ring->mmio_base)); @@ -2662,7 +2665,12 @@ semaphore_waits_for(struct intel_ring_buffer *ring, = u32 *seqno) return NULL; = *seqno =3D ioread32(ring->virtual_start + head + 4) + 1; - return semaphore_wait_to_signaller_ring(ring, ipehr); + if (INTEL_INFO(dev_priv->dev)->gen >=3D 8) { + offset =3D ioread32(ring->virtual_start + head + 12); + offset <<=3D 32; + offset |=3D ioread32(ring->virtual_start + head + 8); + } + return semaphore_wait_to_signaller_ring(ring, ipehr, offset); } = static int semaphore_passed(struct intel_ring_buffer *ring) -- = 1.8.3.2 > return NULL; > } else { > -- = > 1.9.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC