From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 07/71] drm/i915/chv: Add DPFLIPSTAT register bits for Cherryview Date: Fri, 2 May 2014 11:29:16 +0300 Message-ID: <20140502082916.GS18465@intel.com> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-8-git-send-email-ville.syrjala@linux.intel.com> <4B498744C37F034EA16F6FBC6AB9FAD2014D11B7@IRSMSX103.ger.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 19DD26E4C1 for ; Fri, 2 May 2014 01:29:48 -0700 (PDT) Content-Disposition: inline In-Reply-To: <4B498744C37F034EA16F6FBC6AB9FAD2014D11B7@IRSMSX103.ger.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Barbalho, Rafael" Cc: "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org On Thu, May 01, 2014 at 01:55:23PM +0000, Barbalho, Rafael wrote: > > -----Original Message----- > > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Beh= alf > > Of ville.syrjala@linux.intel.com > > Sent: Wednesday, April 09, 2014 11:28 AM > > To: intel-gfx@lists.freedesktop.org > > Subject: [Intel-gfx] [PATCH 07/71] drm/i915/chv: Add DPFLIPSTAT register > > bits for Cherryview > > = > > From: Ville Syrj=E4l=E4 > > = > > CHV has pipe C and PSR which cause changes to DPFLIPSTAT. > > = > > Signed-off-by: Ville Syrj=E4l=E4 > = > If we add the _CHV to some of the bitfield defines would you also add the= m to here? These are also CHV specific. I figured these are pretty clear even w/o the suffix. Everyone ought to know VLV has two pipes and CHV has three. > = > Reviewed-by: Rafael Barbalho > = > > --- > > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ > > 1 file changed, 7 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index 0fb6b6f..81d4b83 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -3451,12 +3451,19 @@ enum punit_power_well { > > #define SPRITED_FLIP_DONE_INT_EN (1<<26) > > #define SPRITEC_FLIP_DONE_INT_EN (1<<25) > > #define PLANEB_FLIP_DONE_INT_EN (1<<24) > > +#define PIPE_PSR_INT_EN (1<<22) > > #define PIPEA_LINE_COMPARE_INT_EN (1<<21) > > #define PIPEA_HLINE_INT_EN (1<<20) > > #define PIPEA_VBLANK_INT_EN (1<<19) > > #define SPRITEB_FLIP_DONE_INT_EN (1<<18) > > #define SPRITEA_FLIP_DONE_INT_EN (1<<17) > > #define PLANEA_FLIPDONE_INT_EN (1<<16) > > +#define PIPEC_LINE_COMPARE_INT_EN (1<<13) > > +#define PIPEC_HLINE_INT_EN (1<<12) > > +#define PIPEC_VBLANK_INT_EN (1<<11) > > +#define SPRITEF_FLIPDONE_INT_EN (1<<10) > > +#define SPRITEE_FLIPDONE_INT_EN (1<<9) > > +#define PLANEC_FLIPDONE_INT_EN (1<<8) > > = > > #define DPINVGTT (VLV_DISPLAY_BASE + > > 0x7002c) /* VLV only */ > > #define CURSORB_INVALID_GTT_INT_EN (1<<23) > > -- > > 1.8.3.2 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC