From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 04/71] drm/i915/chv: Flush caches when programming page tables Date: Tue, 6 May 2014 21:16:04 +0200 Message-ID: <20140506191604.GB5730@phenom.ffwll.local> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-5-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f44.google.com (mail-ee0-f44.google.com [74.125.83.44]) by gabe.freedesktop.org (Postfix) with ESMTP id 32AA06E3E8 for ; Tue, 6 May 2014 12:16:09 -0700 (PDT) Received: by mail-ee0-f44.google.com with SMTP id c41so54066eek.3 for ; Tue, 06 May 2014 12:16:08 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1397039349-10639-5-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 09, 2014 at 01:28:02PM +0300, ville.syrjala@linux.intel.com wro= te: > From: Rafael Barbalho > = > Page table updates were getting stuck in the CPU cache on chv causing > spurious page faults and strange behaviour. > = > Signed-off-by: Rafael Barbalho > [vsyrjala: Add !HAS_LLC checks] > Signed-off-by: Ville Syrj=E4l=E4 Reviewed this myself. Poke for the gen7/byt version of this ... -Daniel > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i= 915_gem_gtt.c > index 3e4d1f0..ba51901 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -267,6 +267,8 @@ static void gen8_ppgtt_clear_range(struct i915_addres= s_space *vm, > num_entries--; > } > = > + if (!HAS_LLC(ppgtt->base.dev)) > + drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); > kunmap_atomic(pt_vaddr); > = > pte =3D 0; > @@ -303,6 +305,8 @@ static void gen8_ppgtt_insert_entries(struct i915_add= ress_space *vm, > gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), > cache_level, true); > if (++pte =3D=3D GEN8_PTES_PER_PAGE) { > + if (!HAS_LLC(ppgtt->base.dev)) > + drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); > kunmap_atomic(pt_vaddr); > pt_vaddr =3D NULL; > if (++pde =3D=3D GEN8_PDES_PER_PAGE) { > @@ -312,8 +316,11 @@ static void gen8_ppgtt_insert_entries(struct i915_ad= dress_space *vm, > pte =3D 0; > } > } > - if (pt_vaddr) > + if (pt_vaddr) { > + if (!HAS_LLC(ppgtt->base.dev)) > + drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); > kunmap_atomic(pt_vaddr); > + } > } > = > static void gen8_free_page_tables(struct page **pt_pages) > @@ -576,6 +583,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgt= t, uint64_t size) > pd_vaddr[j] =3D gen8_pde_encode(ppgtt->base.dev, addr, > I915_CACHE_LLC); > } > + if (!HAS_LLC(ppgtt->base.dev)) > + drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); > kunmap_atomic(pd_vaddr); > } > = > -- = > 1.8.3.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch