From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH v2 09/71] drm/i915/chv: Add DPINVGTT registers defines for Cherryview Date: Tue, 6 May 2014 21:20:30 +0200 Message-ID: <20140506192030.GC5730@phenom.ffwll.local> References: <4B498744C37F034EA16F6FBC6AB9FAD2014D11E6@IRSMSX103.ger.corp.intel.com> <1399019751-22631-1-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f41.google.com (mail-ee0-f41.google.com [74.125.83.41]) by gabe.freedesktop.org (Postfix) with ESMTP id CFCCA6E849 for ; Tue, 6 May 2014 12:20:34 -0700 (PDT) Received: by mail-ee0-f41.google.com with SMTP id t10so53440eei.28 for ; Tue, 06 May 2014 12:20:34 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1399019751-22631-1-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, May 02, 2014 at 11:35:51AM +0300, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > Due to Pipe C DPINVGTT has more bits on CHV. > = > v2: Fix comment to say VLV/CHV (Rafael) > = > Reviewed-by: Rafael Barbalho > Signed-off-by: Ville Syrj=E4l=E4 Merged up to this one to dinq. -Daniel > --- > drivers/gpu/drm/i915/i915_reg.h | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 12fa93a..666c1d0 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3494,7 +3494,11 @@ enum punit_power_well { > #define SPRITEE_FLIPDONE_INT_EN (1<<9) > #define PLANEC_FLIPDONE_INT_EN (1<<8) > = > -#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */ > +#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ > +#define SPRITEF_INVALID_GTT_INT_EN (1<<27) > +#define SPRITEE_INVALID_GTT_INT_EN (1<<26) > +#define PLANEC_INVALID_GTT_INT_EN (1<<25) > +#define CURSORC_INVALID_GTT_INT_EN (1<<24) > #define CURSORB_INVALID_GTT_INT_EN (1<<23) > #define CURSORA_INVALID_GTT_INT_EN (1<<22) > #define SPRITED_INVALID_GTT_INT_EN (1<<21) > @@ -3504,6 +3508,11 @@ enum punit_power_well { > #define SPRITEA_INVALID_GTT_INT_EN (1<<17) > #define PLANEA_INVALID_GTT_INT_EN (1<<16) > #define DPINVGTT_EN_MASK 0xff0000 > +#define DPINVGTT_EN_MASK_CHV 0xfff0000 > +#define SPRITEF_INVALID_GTT_STATUS (1<<11) > +#define SPRITEE_INVALID_GTT_STATUS (1<<10) > +#define PLANEC_INVALID_GTT_STATUS (1<<9) > +#define CURSORC_INVALID_GTT_STATUS (1<<8) > #define CURSORB_INVALID_GTT_STATUS (1<<7) > #define CURSORA_INVALID_GTT_STATUS (1<<6) > #define SPRITED_INVALID_GTT_STATUS (1<<5) > @@ -3513,6 +3522,7 @@ enum punit_power_well { > #define SPRITEA_INVALID_GTT_STATUS (1<<1) > #define PLANEA_INVALID_GTT_STATUS (1<<0) > #define DPINVGTT_STATUS_MASK 0xff > +#define DPINVGTT_STATUS_MASK_CHV 0xfff > = > #define DSPARB 0x70030 > #define DSPARB_CSTART_MASK (0x7f << 7) > -- = > 1.8.3.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch