From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 1/9] drm/i915: Use topdown allocation for PPGTT PDEs on gen6/7 Date: Wed, 7 May 2014 09:44:07 +0200 Message-ID: <20140507074407.GM5730@phenom.ffwll.local> References: <1399440098-17378-1-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f47.google.com (mail-ee0-f47.google.com [74.125.83.47]) by gabe.freedesktop.org (Postfix) with ESMTP id C3C8A6E4A5 for ; Wed, 7 May 2014 00:44:11 -0700 (PDT) Received: by mail-ee0-f47.google.com with SMTP id c13so402178eek.20 for ; Wed, 07 May 2014 00:44:11 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1399440098-17378-1-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ben Widawsky Cc: Intel GFX , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Tue, May 06, 2014 at 10:21:30PM -0700, Ben Widawsky wrote: > It was always the intention to do the topdown allocation for context > objects (Chris' idea originally). Unfortunately, I never managed to land > the patch, but someone else did, so now we can use it. > > As a reminder, hardware contexts never need to be in the precious GTT > aperture space - which is what is what happens with the normal bottom up > allocation we do today. Doing a top down allocation increases the odds > that the HW contexts can get out of the way, especially with per FD > contexts as is done in full PPGTT > > Signed-off-by: Ben Widawsky Queued for -next, thanks for the patch. -Daniel > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index f6354e0..66fcfc9 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -1035,8 +1035,7 @@ alloc: > &ppgtt->node, GEN6_PD_SIZE, > GEN6_PD_ALIGN, 0, > 0, dev_priv->gtt.base.total, > - DRM_MM_SEARCH_DEFAULT, > - DRM_MM_CREATE_DEFAULT); > + DRM_MM_TOPDOWN); > if (ret == -ENOSPC && !retried) { > ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, > GEN6_PD_SIZE, GEN6_PD_ALIGN, > -- > 1.9.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch