From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface. Date: Wed, 7 May 2014 17:08:44 +0300 Message-ID: <20140507140844.GI18465@intel.com> References: <1399294059-20748-1-git-send-email-deepak.s@linux.intel.com> <1399294059-20748-3-git-send-email-deepak.s@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 9CC346E531 for ; Wed, 7 May 2014 07:09:13 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1399294059-20748-3-git-send-email-deepak.s@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: deepak.s@linux.intel.com Cc: intel-gfx@lists.freedesktop.org, fafael.barbalho@intel.com List-Id: intel-gfx@lists.freedesktop.org On Mon, May 05, 2014 at 06:17:31PM +0530, deepak.s@linux.intel.com wrote: > From: Deepak S > = > In BDW, Apart from unmasking up/down threshold interrupts. we need > to umask bit 32 of PM_INTRMASK to route interrupts to target via Display > Interface. > = > v2: Add (1<<31) mask (Ville) > = > Signed-off-by: Deepak S > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 2 ++ > 2 files changed, 3 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index ca4f8b9..c850254 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5112,6 +5112,7 @@ enum punit_power_well { > #define GEN6_RC6p_THRESHOLD 0xA0BC > #define GEN6_RC6pp_THRESHOLD 0xA0C0 > #define GEN6_PMINTRMSK 0xA168 > +#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) > = > #define GEN6_PMISR 0x44020 > #define GEN6_PMIMR 0x44024 /* rps_lock */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 0e69c97..ebb5c88 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3114,6 +3114,8 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private= *dev_priv, u8 val) > if (INTEL_INFO(dev_priv->dev)->gen <=3D 7 && !IS_HASWELL(dev_priv->dev)) > mask |=3D GEN6_PM_RP_UP_EI_EXPIRED; > = > + mask |=3D GEN8_PMINTR_REDIRECT_TO_NON_DISP; > + Didn't Ben want a gen check here? > return ~mask; > } > = > -- = > 1.9.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC