[PATCH 00/10] Enable RC6/Turbo on CHV

deepak.s
2014-05-05T12:47:48Z

From: Deepak S <deepak.s@linux.intel.com>

Squashed some of the patches and created a new patch series. Addressed review comments on most of the patches.

Ben Widawsky (1):
drm/i915/bdw: Implement a basic PM interrupt handler

Deepak S (7):
drm/i915: Enable PM Interrupts target via Display Interface.
drm/i915/chv: Enable Render Standby (RC6) for Cherryview
drm/i915/chv: Added CHV specific register read and write
drm/i915/chv: Streamline CHV forcewake stuff
drm/i915/chv: Enable RPS (Turbo) for Cherryview
drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
drm/i915/chv: Freq(opcode) request for CHV.

Ville Syrjälä (2):
drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV

drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_irq.c | 84 ++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 17 +++
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 259 ++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_sideband.c | 15 ++
drivers/gpu/drm/i915/intel_uncore.c | 146 ++++++++++++++++---
7 files changed, 491 insertions(+), 34 deletions(-)

--
1.9.1

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