Re: [PATCH 1/2] rendercopy/bdw: Enable hw-generated binding tables

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Wed, May 07, 2014 at 11:59:23PM +0300, Abdiel Janulgue wrote:
> On Wednesday, May 07, 2014 02:49:31 PM Ville Syrjälä wrote:
> > I quickly cobbled together a hsw version of this and gave it a whirl on
> > one machine. Seems to work just fine here, and no lockups when switching
> > between hw and sw binding tables. Did you get the lockups on hsw even
> > with rendercopy?
> > 
> > Here's my hsw version:
> > 
> > 
> > +static void
> > +gen7_hw_binding_table(struct intel_batchbuffer *batch, bool enable)
> > +{
> > +	if (!enable) {
> > +		OUT_BATCH(MI_RS_CONTROL | 0x0);
> > +
> > +		OUT_BATCH(HSW_3DSTATE_BINDING_TABLE_POOL_ALLOC | (3 - 2));
> > +		/* binding table pool base address */
> 
> This bit I missed and the source of my troubles for the past few months.
> 
> > +		OUT_BATCH(3 << 5);
> 
> Yep, I confirm toggling on HSW does work quite well now. I'll now update the 
> patches to include HSW path on the kernel. I also take back my previous 
> statement that RS is broken on HSW! :)

Excellent.

I was wondering a bit if we need to make the kernel turn off the hw
binding tables between batches, but since we now have per fd default
contexts and 3DSTATE_BINDING_TABLE_POOL_ALLOC should be saved in the
context, maybe we don't actually need to do that. Although it seems
like that would cause problems when we switch to the global default
context since we use the restore_inhibit flag there. So maybe we need
to special case the default context here and force the hw binding
tables off when switching to it.

Would be nice to have some igts for this to test how things work when
you combine rs vs. no-rs in different ways using single context,
multiple contexts, and multiple fds.

> 
> Thanks a lot Ville!

I'm glad I could help.

> 
> 
> > +		/* Upper bound */
> > +		OUT_BATCH(0);
> > +
> > +		OUT_BATCH(GEN7_PIPE_CONTROL | (4 - 2));
> > +		OUT_BATCH(GEN7_PIPE_CONTROL_CS_STALL |
> > GEN7_PIPE_CONTROL_STALL_AT_SCOREBOARD); +		OUT_BATCH(0);
> > +		OUT_BATCH(0);
> > +
> > +		OUT_BATCH(GEN7_PIPE_CONTROL | (4 - 2));
> > +		OUT_BATCH(GEN7_PIPE_CONTROL_SC_INVALIDATE);
> > +		OUT_BATCH(0);
> > +		OUT_BATCH(0);
> > +
> > +		return;
> > +        }

-- 
Ville Syrjälä
Intel OTC