From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 3/4] drm/i915: Kill vblank waits after pipe
 enable on gmch platforms
Date: Fri, 9 May 2014 12:09:46 +0300
Message-ID: <20140509090946.GS18465@intel.com>
References: <1399566196-25086-1-git-send-email-ville.syrjala@linux.intel.com>
 <1399566196-25086-4-git-send-email-ville.syrjala@linux.intel.com>
 <20140509060309.GH3443@nuc-i3427.alporthouse.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mga09.intel.com (mga09.intel.com [134.134.136.24])
 by gabe.freedesktop.org (Postfix) with ESMTP id 7DB8B6E079
 for <intel-gfx@lists.freedesktop.org>; Fri,  9 May 2014 02:10:02 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <20140509060309.GH3443@nuc-i3427.alporthouse.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Fri, May 09, 2014 at 07:03:09AM +0100, Chris Wilson wrote:
> On Thu, May 08, 2014 at 07:23:15PM +0300, ville.syrjala@linux.intel.com w=
rote:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > The pipe might not start to actually run until the port has been enabled
> > (depends on the platform and port type). So don't try to wait for vblank
> > after we enabled the pipe but haven't yet enabled the port.
> =

> I am pretty sure those waits were in the docs. Pretty sure, not certain
> though.

I didn't find them anywhere. The only vblank waits I see are the ones
for gen2 between disabling the planes and the pipe since the pipe
disable isn't double buffered on vblank. And that wait is still there
due to intel_disable_primary_hw_plane(). If my mmio vs. CS flip race
series ever gets reviewed that also gets killed, but I do add back an
explicit vblank wait for gen2 only into i9xx_crtc_disable().

-- =

Ville Syrj=E4l=E4
Intel OTC