From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH v3] drm/i915: Added write-enable pte bit
 support
Date: Wed, 14 May 2014 00:30:34 +0200
Message-ID: <20140513223034.GX3908@phenom.ffwll.local>
References: <1392108543-31552-1-git-send-email-akash.goel@intel.com>
 <20140513150524.4050090c@jbarnes-desktop>
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To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: akash.goel@intel.com, intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Tue, May 13, 2014 at 03:05:24PM -0700, Jesse Barnes wrote:
> On Tue, 11 Feb 2014 14:19:03 +0530
> akash.goel@intel.com wrote:
> 
> > @@ -810,6 +815,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
> >  		pt_vaddr[act_pte] =
> >  			vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
> >  				       cache_level, true);
> > +
> >  		if (++act_pte == I915_PPGTT_PT_ENTRIES) {
> >  			kunmap_atomic(pt_vaddr);
> >  			pt_vaddr = NULL;
> 
> Some extra whitespace here.
> 
> Otherwise:
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Hm, looking at the patch again encoding this into the cache_level enum is
fraught with fun. And due to IS_VLV aliasing chv this will blow up on chv
very likely. My old idea was to eventually add a pte_flags param all over
for this stuff with additional bits.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch